Response times based on application states

Patent metadata

Field	Value
Publication number	US-10324752-B2
Application number	US-201715608260-A
Country	US
Kind code	B2
Filing date	May 30, 2017
Priority date	May 30, 2017
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

Systems and methods for improving response times in based on application states. In some embodiments, an Information Handling System (IHS) may include a Central Processing Unit (CPU) and a hardware memory storage device coupled to the CPU, the hardware memory storage device having program instructions stored thereon that, upon execution by the CPU, configure the IHS to: identify a first state of an application being executed by the CPU at runtime; identify a trigger event configured to cause the IHS to change from the first state to a second state; in response to the trigger event, switch from the first state to a second state, wherein the first state is associated with first hardware configuration and the second state is associated with a second hardware configuration; and in response to the trigger event, switch the first hardware configuration to the second hardware configuration.

First claim

The invention claimed is:

1. An Information Handling System (IHS), comprising:
a Central Processing Unit (CPU); and
a hardware memory storage device coupled to the CPU, the hardware memory storage device having program instructions stored thereon that, upon execution by the CPU, cause the IHS to:
identify a first state of an application being executed by the CPU at runtime;
identify a trigger event configured to cause the IHS to change from the first state to a second state;
in response to the trigger event, switch from the first state to a second state, wherein the first state is associated with first hardware configuration and the second state is associated with a second hardware configuration; and
in response to the trigger event, switch the first hardware configuration to the second hardware configuration, wherein the trigger event belongs to a profile that stores, for the trigger event, an identification of a bottleneck and the second hardware configuration.

2. The IHS of claim 1 , wherein at least one of the trigger events is selected from the group consisting of: initialize, launch, resize, load, close, rotate, view, exit, resume, switch, auto save, refresh, and run.

3. The IHS of claim 2 , wherein the first and second states are selected from the group consisting of: initializing, launching, resizing, loading, closing, rotating, viewing, exiting, resuming, switching, saving, refreshing, and running.

4. The IHS of claim 1 , wherein the bottleneck includes a CPU bottleneck, and wherein the second hardware configuration includes a number of CPU cores or speed that enables the IHS to respond to a user command received during the second state.

5. The IHS of claim 1 , wherein the bottleneck includes a memory or storage bottleneck, and wherein the second hardware configuration includes a memory allocation or bandwidth that enables the IHS to respond to a user command received during the second state.

6. The IHS of claim 1 , wherein the bottleneck includes a network or communication bottleneck, and wherein the second hardware configuration includes a network priority or bandwidth that enables the IHS to respond to a user command received during the second state.

7. The IHS of claim 1 , wherein the profile further stores a second response time obtainable with the second hardware configuration, wherein a first response time stored in the profile in association with the first state is shorter that the second response time when the application is in the first state, and wherein the second response time is shorter than the first response time when the application is in the second state.

8. The IHS of claim 7 , wherein the program instructions, upon execution, further configure the IHS to, prior to the switch from the first hardware configuration to the second hardware configuration, determine that an overhead time associated with the switching when the application is in the first state is smaller than a difference between the second response time and the first response time when the application is in the second state.

9. The IHS of claim 1 , wherein the program instructions, upon execution, further configure the IHS to switch from the second hardware configuration to the first hardware configuration in response to a return from the second state to the first state.

10. A hardware memory storage device coupled to a processor of an Information Handling System (IHS), the hardware memory storage device having program instructions stored thereon that, upon execution by the processor, cause the IHS to:
identify a first state of an application being executed by the CPU at runtime;
identify a trigger event configured to cause the IHS to change from the first state to a second state;
in response to the trigger event, switch from the first state to a second state, wherein the first state is associated with first hardware configuration and the second state is associated with a second hardware configuration; and
in response to the trigger event, switch the first hardware configuration to the second hardware configuration, wherein the trigger event belongs to a profile that stores, for the trigger event, an identification of a bottleneck and the second hardware configuration.

11. The hardware memory storage device of claim 10 , wherein the bottleneck includes a CPU bottleneck, and wherein the second hardware configuration includes a number of CPU cores or speed that enables the IHS to respond to a user command received during the second state.

12. The hardware memory storage device of claim 10 , wherein the bottleneck includes a memory or storage bottleneck, and wherein the second hardware configuration includes a memory allocation or bandwidth that enables the IHS to respond to a user command received during the second state.

13. The hardware memory storage device of claim 10 , wherein the bottleneck includes a network or communication bottleneck, and wherein the second hardware configuration includes a network priority or bandwidth that enables the IHS to respond to a user command received during the second state.

14. The hardware memory storage device of claim 10 , wherein the profile further stores a second response time obtainable with the second hardware configuration, wherein the second response time is shorter, during the second state, than a first response time obtainable during the first state, and wherein the program instructions, upon execution, further configure the IHS to, prior to the switch, determine that an overhead time associated with the switch is smaller than a difference between the second response time and the first response time.

15. A method comprising:
identifying a first state of an application being executed by the CPU at runtime;
identifying a trigger event configured to cause the IHS to change from the first state to a second state;
in response to the trigger event, switching from the first state to a second state, wherein the first state is associated with first hardware configuration and the second state is associated with a second hardware configuration; and
in response to the trigger event, switching the first hardware configuration to the second hardware configuration, wherein the trigger event belongs to a profile that stores, for the trigger event, an identification of a bottleneck and the second hardware configuration.

16. The method of claim 15 , wherein: (a) the bottleneck includes a CPU bottleneck and the second hardware configuration includes a number of CPU cores or speed; (b) the bottleneck includes a memory or storage bottleneck, and the second hardware configuration includes a memory allocation or bandwidth; or (c) the bottleneck includes a network or communication bottleneck, and the second hardware configuration includes a network priority or bandwidth.

17. The method of claim 15 , wherein the profile further stores a second response time obtainable with the second hardware configuration, wherein the second response time is shorter, during the second state, than a first response time obtainable during the first state, and wherein the method further comprises, prior to the switch, determining that an overhead time associated with the switch is smaller than a difference between the second response time and the first response time.

Assignees

• Dell Products Lp

Inventors

• Khosrowpour Farzad
• Markow Mitchell Anthony

Classifications

• G06F9/4831 Primary

  with variable priority · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/5038

  considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups) · CPC title

• G06F9/5005

  to service a request · CPC title