Programmable logic controller system

Patent metadata

Field	Value
Publication number	US-10324440-B2
Application number	US-201615188897-A
Country	US
Kind code	B2
Filing date	Jun 21, 2016
Priority date	Jun 22, 2015
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

In some embodiments, a PLC system including a first CPU comprising a first media access control (MAC) communications layer and configured to generate data necessary for operation of the CPU, perform control operation based on the generated data, and transmit the generated data to a second CPU via the first MAC communications layer is included. The PLC system may further include the second CPU comprising a second MAC communications layer receiving the generated data via the first MAC communications layer and configured to perform service operation based on the received data. The first CPU may be connected to a memory in which data to be transmitted to the second CPU is stored at a predetermined location, and the second CPU may receive the data stored in the predetermined location of the memory by a direct memory access (DMA) scheme.

First claim

What is claimed is:

1. A programmable logic controller (PLC) system comprising:
a control CPU including a first media access control (MAC) communications layer; and
a service CPU including a second MAC communications layer,
the control CPU configured to generate a first data for a control operation of the control CPU and a second data for a service operation of the service CPU, perform the control operation on a system at a lower hierarchical level based on the first data, and transmit the second data to the service CPU via the first MAC communications layer, and
the service CPU configured to generate the first data and the second data, perform the service operation except the control operation based on the second data and transmit the first data to the control CPU via the second MAC communications layer,
wherein the service CPU is connected to a service memory in which the first data to be transmitted to the control CPU is stored at a first predetermined location, and the control CPU acquires the first data stored in the first predetermined location of the service memory by a direct memory access (DMA) scheme, and
wherein the control CPU is connected to a control memory in which the second data to be transmitted to the service CPU is stored at a second predetermined location, and the service CPU acquires the second data stored in the second predetermined location of the control memory by the DMA scheme.

2. The PLC system of claim 1 , wherein the service CPU receives the second data from the control CPU via the first and second MAC communications layers based on Ethernet scheme.

3. The PLC system of claim 2 , wherein the service CPU comprises an Ethernet control module acquiring the second data.

4. The PLC system of claim 1 , wherein the control operation comprises at least one of logic control, motion control, time synchronization control, communications control and input/output control operations.

5. The PLC system of claim 1 , wherein the service operation is further configured to provide IT service and/or additional service.

6. The PLC system of claim 5 , further comprising a third CPU configured to provide security service in the PLC system.

Assignees

• Lsis Co Ltd

Inventors

• Yoon Geon
• Kim Ki-Myung

Classifications

• G05B2219/1205

  Memory access for different processors, memory arbitration, mailbox · CPC title

• G05B2219/15112

  Two cpu control plc, select cpu, video switch, with special key · CPC title

• H04L69/324

  in the data link layer [OSI layer 2], e.g. HDLC · CPC title

• G05B19/056 Primary

  Programming the PLC · CPC title

• G05B19/052 Primary

  Linking several PLC's · CPC title