Method of forming an integrated circuit and related integrated circuit

Patent metadata

Field	Value
Publication number	US-10324256-B2
Application number	US-201715837173-A
Country	US
Kind code	B2
Filing date	Dec 11, 2017
Priority date	Jan 14, 2014
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.

First claim

The invention claimed is:

1. An integrated circuit comprising:
at least one transistor arranged in a partially processed CMOS device layer; and
at least a pair of optoelectronic devices adapted to be coupled by a waveguide to define an optical interconnect on a semiconductor substrate which is arranged adjacent to the partially processed CMOS device layer,
wherein the optoelectronic devices are configured to be electrically connected to the at least one transistor through at least one via formed in the partially processed CMOS device layer and the semiconductor substrate, and the optoelectronic devices are formed from at least a first wafer material different to silicon, and
wherein the waveguide is formed from a second wafer material deposited in a first recess formed in the first wafer material.

2. The integrated circuit of claim 1 , wherein the first wafer material different to silicon includes a group III-V semiconductor material or an organic material.

3. The integrated circuit of claim 2 , wherein the group III-V semiconductor material includes GaN, InGaP, GaAs, AlGaAs or InGaAs.

4. The integrated circuit of claim 1 , wherein the integrated circuit is formed as a single processor or a portion of a processor.

5. The integrated circuit of claim 1 , wherein the optical interconnect is arranged below the partially processed CMOS device layer.

6. The integrated circuit of claim 1 , wherein the second wafer material includes silicon nitride.

7. The integrated circuit of claim 1 , wherein the optoelectronic devices have different structures, and
wherein one of the optoelectronic devices includes an InGaN layer on top of and separated from an InGaN MQW layer.

8. The integrated circuit of claim 1 , wherein the at least one transistor comprises a first transistor and a second transistor configured to communicate with one another through the optical interconnect.

Assignees

• Massachusetts Inst Technology
• Nat Univ Singapore
• Univ Nanyang Tech

Inventors

• Zhang Wenjia
• Wang Bing
• Zhang Li
• Zhu Zhaomin
• Michel Jurgen
• Chua Soo-Jin
• Peh Li-Shiuan
• Chiah Siau Ben
• Lee Eng Kian Kenneth

Classifications

• G02B6/12002

  Three-dimensional structures · CPC title

• G02B6/136

  by etching · CPC title

• G02B6/12004 Primary

  Combinations of two or more optical elements · CPC title

• G02B6/428

  containing printed circuit boards [PCB] · CPC title

• Y02E10/544

  Solar cells from Group III-V materials · CPC title