Current sense amplifier with enhanced common mode input range

Patent metadata

Field	Value
Publication number	US-10324113-B2
Application number	US-201615069733-A
Country	US
Kind code	B2
Filing date	Mar 14, 2016
Priority date	Nov 17, 2015
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

The overall performance of a current sense amplifier system may be improved by increasing the common mode rejection of the system. In particular, improved current sense amplifiers may be configured to use a first signal path coupled to the amplifier and a first input terminal, wherein the first signal path is configured to measure the current through a device by generating a voltage proportional to the measured current, wherein the generated voltage includes a small signal voltage with a large common mode voltage, and a second signal path coupled to the amplifier and the first input terminal, wherein the second signal path is configured to reduce the common mode of the generated voltage by level shifting the generated voltage to reduce the common mode voltage.

First claim

What is claimed is:

1. An apparatus for measuring a current through a device, comprising:
a first analog-to-digital conversion (ADC) path comprising:
an amplifier;
a first signal path coupled to the amplifier and a first input terminal, wherein the first signal path is configured to measure the current through a device by generating a voltage proportional to the measured current, wherein the generated voltage comprises a small signal voltage with a large common mode voltage;
a second signal path coupled to the amplifier and the first input terminal, wherein the second signal path is configured to reduce the common mode of the generated voltage by level shifting the generated voltage to reduce the common mode voltage; and
an analog-to-digital converter coupled to an output of the amplifier.

2. The apparatus of claim 1 , wherein the first signal path comprises:
a first resistor coupled between the first input terminal and a first input of the amplifier; and
a second resistor coupled between the first input terminal and a second input of the amplifier.

3. The apparatus of claim 1 , wherein the second signal path comprises:
an inverter coupled to the first input terminal;
a first resistor coupled between the inverter and a first input of the amplifier; and
a second resistor coupled between the inverter and a second input of the amplifier.

4. The apparatus of claim 1 , wherein the first signal path comprises a first passive R-C filter, and wherein the second signal path comprises a second passive R-C filter, wherein the first passive R-C filter and the second passive R-C filter are configured to band limit the common mode voltage signal.

5. The apparatus of claim 4 , further comprising:
a second amplifier coupled to the device;
a third signal path from the device to the second amplifier, wherein the third signal path comprises a third passive R-C filter; and
a fourth signal path from the first input terminal to the second amplifier, wherein the fourth signal path comprises a fourth passive R-C filter.

6. The apparatus of claim 1 , wherein the apparatus further comprises:
a second ADC path configured to measure a common mode value; and
a memory element comprising a stored calibration value.

7. The apparatus of claim 6 , further comprising:
a first external resistor coupled between the first ADC path and the first input terminal; and
a second external resistor coupled between the second ADC path and the device, wherein the first external resistor and the second external resistor are configured to increase linearity of the first ADC path and the second ADC path, respectively.

8. The apparatus of claim 1 , wherein the device comprises a transducer.

9. A method, comprising:
receiving, through a first signal path, a signal for measuring a current through a device, wherein the signal comprises a small signal with a large common mode;
shifting, through a second signal path, a level of the signal without changing other characteristics of the signal such that the common mode of the signal is reduced; and
sensing the current through the device,
wherein the steps of receiving the signal and shifting the level of the signal are performed in a first analog-to-digital conversion (ADC) path comprising an analog-to-digital converter.

10. The method of claim 9 , wherein shifting the level through the second signal path comprises inverting the signal.

11. The method of claim 9 , wherein receiving the signal through the first signal path comprises filtering the signal with a first passive R-C filter, wherein passive R-C filtering is also applied in the second signal path with a second passive R-C filter, and wherein the first passive R-C filter and the second passive R-C filter are configured to band limit the common mode.

12. The method of claim 9 , wherein the method further comprises:
monitoring a common mode value for the device with a second ADC path;
receiving, from a memory element, a stored calibration value; and
correcting a voltage proportional to the sensed current based, at least in part, on the measured common mode value and the stored calibration value.

13. The method of claim 12 , wherein a voltage generated based on the sensed current through the device comprises a small signal voltage having an amplitude smaller than the common mode value.

14. The method of claim 12 , wherein the step of correcting the voltage proportional to the sensed current value comprises correcting for a resistor mismatch in the first ADC path.

15. The method of claim 9 , wherein the step of sensing the current through the device comprises sensing the current through a transducer.

16. A mobile device, comprising:
a transducer; and
a controller integrated circuit (IC) coupled to the transducer, wherein the controller IC is configured to measure a current through the transducer, the controller IC comprising:
a first analog-to-digital conversion (ADC) path comprising:
an amplifier coupled to the transducer;
a first input terminal;
a first signal path coupled to the amplifier and the first input terminal, wherein the first signal path is configured to measure the current through the transducer by generating a voltage proportional to the measured current, wherein the generated voltage comprises a small signal voltage with a large common mode voltage;
a second signal path coupled to the amplifier and the first input terminal, wherein the second signal path is configured to reduce the common mode of the generated voltage by level shifting the generated voltage to reduce the common mode voltage; and
an analog-to-digital converter coupled to an output of the amplifier.

17. The apparatus of claim 16 , wherein the first signal path comprises:
a first resistor coupled between the first input terminal and a first input of the amplifier; and
a second resistor coupled between the first input terminal and a second input of the amplifier, and
wherein the second signal path comprises:
an inverter coupled to the first input terminal;
a third resistor coupled between the inverter and a first input of the amplifier; and
a fourth resistor coupled between the inverter and a second input of the amplifier.

18. The apparatus of claim 16 , wherein the first signal path comprises a first passive R-C filter, and wherein the second signal path comprises a second passive R-C filter, wherein the first passive R-C filter and the second passive R-C filter are configured to band limit the common mode voltage signal.

19. The apparatus of claim 16 , further comprising:
a second amplifier coupled to the transducer;
a third signal path from the device to the second amplifier, wherein the third signal path comprises a third passive R-C filter; and
a fourth signal path from the first input terminal to the second amplifier, wherein the fourth signal path comprises a fourth passive R-C filter.

20. The apparatus of claim 16 , wherein the value; and
a memory element comprising a stored calibration apparatus further comprises:
a second ADC path configured to measure a common mode value.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Parupalli Vamsikrishna
• Tyagi Itisha

Classifications

• G01R19/10 Primary

  Measuring sum, difference or ratio · CPC title

• H03F2203/45101

  Control of the DC level being present · CPC title

• H03F1/0205

  in transistor amplifiers · CPC title

• G01R15/14

  Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks · CPC title

• H03F2200/171

  A filter circuit coupled to the output of an amplifier · CPC title