Fail safe clock buffer and clock generator

Patent metadata

Field	Value
Publication number	US-10320509-B2
Application number	US-201514980036-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 28, 2015
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.

First claim

What is claimed is:

1. A fail safe clock generator comprising:
an oscillator circuit configured to generate a clock signal having a short-term stable reference frequency; and
a monitor circuit comprising:
a frequency-to-digital converter configured to generate a first digital frequency value representing a first frequency of a first input clock signal relative to the short-term stable reference frequency;
a circuit configured to provide a second digital frequency value representing a second frequency relative to the short-term stable reference frequency; and
a logic circuit configured to generate a fault detection signal based on a difference between the first digital frequency value and the second digital frequency value,

wherein the fail safe clock generator provides an output clock signal based on the difference.

2. The fail safe clock generator, as recited in claim 1 , wherein the circuit comprises a memory circuit storing a prior first digital frequency value, the second digital frequency value is the prior first digital frequency value, and the second frequency is a prior frequency of the first input clock signal relative to the short-term stable reference frequency.

3. The fail safe clock generator, as recited in claim 1 , wherein the circuit comprises:
a second frequency-to-digital converter configured to generate the second digital frequency value representing the second frequency relative to the short-term stable reference frequency, the second frequency corresponding to a second input clock signal.

4. The fail safe clock generator, as recited in claim 3 , wherein the monitor circuit further comprises:
a third frequency-to-digital converter configured to generate a third digital frequency value representing a third frequency of a third input clock signal relative to the short-term stable reference frequency, the fault detection signal being further based on the third digital frequency value.

5. The fail safe clock generator, as recited in claim 4 , wherein the first input clock signal or the second input clock signal is identified as a faulty clock signal based on the first digital frequency value, the second digital frequency value, and the third digital frequency value.

6. The fail safe clock generator, as recited in claim 1 , wherein the frequency-to-digital converter generates the first digital frequency value based on the first input clock signal, the clock signal having the short-term stable reference frequency, and a digital sensed temperature value.

7. The fail safe clock generator, as recited in claim 1 , further comprising:
a phase-locked loop configured to generate the output clock signal based on an input signal; and
a select circuit responsive to a select signal to select between the first input clock signal and a second input clock signal to be provided as the input signal,
wherein the monitor circuit is further configured to generate the select signal based on the difference, the select signal being configured to select the first input clock signal or the second input clock signal to generate the output clock signal.

8. The fail safe clock generator, as recited in claim 1 , wherein the first input clock signal or a second input clock signal is identified as a faulty clock according to a predetermined difference magnitude threshold value or a predetermined qualification window.

9. The fail safe clock generator, as recited in claim 1 , wherein the monitor circuit further comprises a temperature compensation circuit configured to temperature compensate a relative frequency measurement of the first frequency of the first input clock signal relative to the short-term stable reference frequency based on a digital sensed temperature and predetermined temperature coefficients describing a relationship between temperature and a corresponding frequency of the clock signal.

10. The fail safe clock generator, as recited in claim 1 , wherein the oscillator circuit is a temperature-compensated LC oscillator comprising a passive temperature compensation circuit configured to provide temperature compensation to the temperature-compensated LC oscillator in response to a change in temperature.

11. A method comprising:
generating a clock signal having a short-term stable reference frequency;
generating a first digital frequency value representing a first frequency of a first input clock signal relative to the short-term stable reference frequency;
providing a second digital frequency value representing a second frequency relative to the short-term stable reference frequency;
generating a fault detection signal based on a difference between the first digital frequency value and the second digital frequency value; and
providing an output clock signal based on the difference.

12. The method, as recited in claim 11 , wherein providing the second digital frequency value comprises:
retrieving from memory a prior first digital frequency value, the prior first digital frequency value being provided as the second digital frequency value, and the second frequency being a prior frequency of the first input clock signal relative to the short-term stable reference frequency.

13. The method, as recited in claim 11 , wherein providing the second digital frequency value comprises:
generating the second digital frequency value representing the second frequency relative to the short-term stable reference frequency, the second frequency corresponding to a second input clock signal.

14. The method, as recited in claim 13 , further comprising:
generating a third digital frequency value representing a third frequency of a third input clock signal relative to the short-term stable reference frequency, the fault detection signal being further based on the third digital frequency value.

15. The method, as recited in claim 11 , wherein generating the fault detection signal is further based on a predetermined difference magnitude threshold value or a predetermined qualification window.

16. The method, as recited in claim 11 , further comprising:
generating the output clock signal based on an input signal and a feedback clock signal; and
selecting between the first input clock signal and a second input clock signal to be provided as the input signal in response to the fault detection signal.

17. The method, as recited in claim 11 , further comprising:
generating a digital sensed temperature value indicative of a temperature of an oscillator used to generate the clock signal,
wherein the first digital frequency value is generated based on the first input clock signal, the clock signal having the short-term stable reference frequency, and the digital sensed temperature value.

18. The method, as recited in claim 11 , further comprising:
sensing a temperature of an LC oscillator used to generate the clock signal; and
passively compensating for variations due to changes in the temperature of the LC oscillator.

19. The method, as recited in claim 11 , further comprising:
sensing a temperature of an oscillator used to generate the clock signal,
wherein generating the first digital frequency value includes compensating a relative frequency measurement of the first frequency of the first input clock signal relative to the short-term stable reference frequency based on the temperature and predetermined temperature coefficients describing a relationship between temperature and a corresponding frequency of the clock signal.

20. An apparatus comprising:
means for generating a clock signal having a short-term stab

Assignees

• Silicon Lab Inc

Inventors

• Huang Yunteng
• Eldredge Adam B
• Richmond Gregory J

Classifications

• H04L41/0672

  Electricity · mapped topic

• H04J3/14 Primary

  Monitoring arrangements {(for SDH/SONET rings H04J3/085)} · CPC title

• H04J3/0691

  Synchronisation in a TDM node · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04J3/0688 Primary

  Change of the master or reference, e.g. take-over or failure of the master · CPC title