Superconducting circuits for an A-and-not-B gate having an exclusive-OR gate and an AND gate

Patent metadata

Field	Value
Publication number	US-10320394-B1
Application number	US-201816137731-A
Country	US
Kind code	B1
Filing date	Sep 21, 2018
Priority date	Sep 21, 2018
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Superconducting circuits-based devices and methods for an A-and-not-B gate are provided. In one example, a circuit for an A-and-not-B gate including an output terminal, a first input terminal for receiving a first set of single flux quantum (SFQ) pulses, and a second input terminal for receiving a second set of SFQ pulses is provided. The circuit may further include a first stage configured to perform an exclusive-OR operation on the first set of SFQ pulses received via the first input terminal and the second set of SFQ pulses received via the second input terminal to generate an exclusive-OR result. The circuit may further include a second stage, coupled to the first stage, configured to perform an AND operation on the exclusive-OR result and the first set of SFQ pulses received via the first input terminal and provide an output via the output terminal.

First claim

The invention claimed is:

1. A circuit for an A-and-not-B gate comprising:
an output terminal;
a first input terminal for receiving a first set of single flux quantum (SFQ) pulses;
a second input terminal for receiving a second set of SFQ pulses;
a first stage configured to perform an exclusive-OR operation on the first set of SFQ pulses received via the first input terminal and the second set of SFQ pulses received via the second input terminal to generate an exclusive-OR result; and
a second stage, coupled to the first stage, configured to perform an AND operation on the exclusive-OR result and the first set of SFQ pulses received via the first input terminal and provide an output via the output terminal.

2. The circuit of claim 1 , wherein the first stage comprises an escape junction.

3. The circuit of claim 2 , wherein the escape junction comprises a Josephson junction.

4. The circuit of claim 1 , wherein the first stage comprises a first inductor coupled between the first input terminal and a first node, a first Josephson junction coupled between the first node and a ground terminal, and a second inductor coupled between the first node and a second node.

5. The circuit of claim 4 , wherein the first stage further comprises a third inductor coupled between the second input terminal and a third node, a second Josephson junction coupled between the third node and the ground terminal, and an escape junction coupled between the second node and a fourth node.

6. The circuit of claim 5 , wherein the second stage comprises a powered junction coupled between the fourth node and the output terminal.

7. The circuit of claim 6 , wherein the powered junction comprises a bias terminal coupled to an inductor for powering a third Josephson junction coupled between the fourth node and the ground terminal.

8. A method of operating a circuit for an A-and-not-B gate, wherein the circuit including an output terminal, the method comprising:
receiving a first set of single flux quantum (SFQ) pulses via a first input terminal;
receiving a second set of SFQ pulses via a second input terminal;
performing an exclusive-OR operation on the first set of SFQ pulses received via the first input terminal and the second set of SFQ pulses received via the second input terminal to generate an exclusive-OR result; and
performing an AND operation on the exclusive-OR result and the first set of SFQ pulses received via the first input terminal such that the circuit is configured to pass the first set of SFQ pulses to the output terminal only when inputs to the exclusive-OR operation differ and inputs to the AND operation are the same.

9. The method of claim 8 , wherein the exclusive-OR operation is performed using a first stage and the AND operation is performed using a second stage coupled to the first stage.

10. The method of claim 9 , wherein the first stage comprises an escape junction.

11. The method of claim 10 , wherein the escape junction comprises a Josephson junction.

12. The method of claim 9 , wherein the first stage comprises a first inductor coupled between the first input terminal and a first node, a first Josephson junction coupled between the first node and a ground terminal, and a second inductor coupled between the first node and a second node.

13. The method of claim 12 , wherein in the first stage further comprises a third inductor coupled between the second input terminal and a third node, a second Josephson junction coupled between the third node and the ground terminal, and an escape junction coupled between the second node and a fourth node.

14. The method of claim 13 , wherein the second stage comprises a powered junction coupled between the fourth node and the output terminal.

15. The method of claim 14 , wherein the powered junction comprises a bias terminal coupled to an inductor for powering a third Josephson junction coupled between the fourth node and the ground terminal.

16. A circuit for an A-and-not-B gate comprising:
an output terminal;
a first input terminal for receiving a first set of single flux quantum (SFQ) pulses;
a powered junction coupled to the first input terminal;
a second input terminal for receiving a second set of SFQ pulses;
a first stage configured to perform an exclusive-OR operation on the first set of SFQ pulses received via the first input terminal and the second set of SFQ pulses received via the second input terminal to generate an exclusive-OR result;
a second stage, coupled to the first stage, configured to perform an AND operation on the exclusive-OR result and the first set of SFQ pulses received via the first input terminal such that the circuit is configured to pass the first set of SFQ pulses to the output terminal only when inputs to the exclusive-OR operation differ and inputs to the AND operation are the same; and
a powered junction coupled to the output terminal.

17. The circuit of claim 16 , wherein the first stage comprises an escape junction.

18. The circuit of claim 17 , wherein the escape junction comprises a Josephson junction.

19. The circuit of claim 16 , wherein the first stage comprises a first inductor coupled between the first input terminal and a first node, a first Josephson junction coupled between the first node and a ground terminal, and a second inductor coupled between the first node and a second node.

20. The circuit of claim 19 , wherein in the first stage further comprises a third inductor coupled between the second input terminal and a third node, a second Josephson junction coupled between the third node and the ground terminal, and an escape junction coupled between the second node and a fourth node.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Powell Jack R
• Braun Alexander L

Classifications

• H03K19/21 Primary

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03K19/1952

  with electro-magnetic coupling of the control current · CPC title

• H03K19/0008

  Arrangements for reducing power consumption · CPC title

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• H03K19/1954 Primary

  with injection of the control current · CPC title