Integrative resistive memory in backend metal layers

Patent metadata

Field	Value
Publication number	US-10319908-B2
Application number	US-201514636363-A
Country	US
Kind code	B2
Filing date	Mar 3, 2015
Priority date	May 1, 2014
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries.

First claim

What is claimed is:

1. A method for forming a resistive memory cell, comprising:
providing a semiconductor substrate having a plurality of complementary metal oxide semiconductor (CMOS) devices formed thereon, and having a plurality of exposed copper conductor contact regions;
forming a blocking layer over the semiconductor substrate and in physical contact with copper material of the copper conductor contact regions, wherein the blocking layer is configured to mitigate or prevent diffusion of the copper material through the blocking layer;
forming a plurality of bottom electrodes within the blocking layer and in electrical contact with respective ones of at least a subset of the copper conductor contact regions, a bottom electrode of the plurality of bottom electrodes having a first width;
disposing a set of resistive memory cell layers above the blocking layer, comprising:
disposing a resistive switching material layer above and in physical contact with the plurality of bottom electrodes, and
disposing an active metal material layer above and in physical contact with the resistive switching material layer;

disposing and patterning an etch stop layer and forming discrete etch stop segments over portions of the active metal material layer, wherein the etch stop layer is in physical contact with the active metal material layer and an etch stop segment of the discrete etch stop segments overlying the bottom electrode has a second width larger than the first width;
etching the set of resistive memory cell layers between the discrete etch stop segments to form a plurality of resistive memory structures, wherein respective resistive memory structures comprise the resistive switching material layer, the active metal material layer, and the etch stop layer and a resistive memory structure of the plurality of resistive memory structures overlying the bottom electrode has the second width larger than the first width;
depositing a first dielectric layer above and between the plurality of resistive memory structures;
etching the first dielectric layer to expose top surfaces of the respective etch stop layers of the plurality of resistive memory structures resulting in a top surface of the first dielectric layer to be substantially coplanar to the exposed top surfaces of the respective etch stop layers;
depositing a second dielectric layer above at least a portion of the first dielectric layer and above and in physical contact with the top surface of the first dielectric layer and with the exposed top surfaces of the respective etch stop layers of the plurality of resistive memory structures;
forming and patterning a mask layer above discrete mask portions of the second dielectric layer;
etching at least a portion of the second dielectric layer in response to the mask layer to form a plurality of contact vias, wherein contact vias of the plurality of contact vias expose at least respective portions of the etch stop layers of the plurality of resistive memory structures; and
forming respective copper metal layers within the plurality of contact vias, wherein the copper metal layers are respectively in electrical contact with the portions of the etch stop layers of the plurality of resistive memory structures.

2. The method of claim 1 , wherein a resistive switching material of the resistive switching material layer is selected from a group consisting of: undoped amorphous silicon, non-crystalline silicon, and non-stoichiometric silicon oxide.

3. The method of claim 1 , wherein an active metal material of the active metal material layer is selected from a group consisting of: silver metal or alloy, copper metal or alloy suitable for etching, aluminum metal or alloy, and gold metal or alloy.

4. The method of claim 1 , wherein the disposing the set of resistive memory cell layers further comprises depositing respective two-terminal volatile selection devices above and in electrical series contact with the active metal material layer, wherein the selection devices are formed from a layer comprising at least one of Cu, Al, Ti, W, Ag, Ni, a solid electrolyte, a silicon sub-oxide, Al 2 O 3 , HfO 2 , or ZnO.

5. The method of claim 1 , further comprising:
forming and patterning a second mask layer above an additional discrete mask portion of the second dielectric layer, the additional discrete mask portion being adjacent to and in contact with one of the contact vias; and
etching at least a portion of the first dielectric layer and the second dielectric layer in response to the second mask layer to form a vertical via in the second dielectric layer, the first dielectric layer, and the blocking layer to expose at least a portion of one of another subset of the copper conductor contact regions distinct from the subset; wherein forming the respective copper metal layers within the plurality of contact vias further comprises filling the vertical via with a copper metal contacting the portion of the one of the other subset of the copper conductor contact regions.

6. The method of claim 1 , further comprising forming a barrier layer within the plurality of contact vias interposed between the copper metal layer, and the second dielectric layer and respective etch stop layers.

7. The method of claim 1 , wherein forming the plurality of bottom electrodes within the blocking layer further comprises:
forming a set of via grooves within the blocking layer of the semiconductor substrate;
filling the set of via grooves with a conductive material selected from a group consisting of: doped polysilicon, doped polycrystalline SiGe, Si, TiN, TaN, Pt and Cu;
planarizing the blocking layer and filled via grooves to expose a top surface of the blocking layer and of the conductive material.

8. The method of claim 1
wherein the disposing the set of resistive memory cell layers further comprises disposing respective two-terminal volatile selection devices above and in electrical series contact with the active material layer;
wherein disposing the respective two-terminal volatile selection devices comprises:
forming a first selection electrode;
forming a volatile switching layer above and in contact with the first selection electrode; and
forming a second selection electrode above and in contact with the volatile switching layer.

9. The method of claim 8 wherein the forming the first selection electrode comprises forming a layer of material selected from a group consisting of: a silver compound, a metal-oxide alloy, and a copper compound.

10. The method of claim 8 wherein the forming the volatile switching layer comprises forming a layer of material selected from a group consisting of: a non-stoichiometric metal-oxide, a non-stoichiometric metal-nitride, and a non-stoichiometric silicon sub-oxide.

11. The method of claim 1 wherein providing the semiconductor substrate comprises forming the plurality of exposed copper conductor contact regions on top of the semiconductor substrate, wherein the exposed copper conductor contact regions comprise a backend metal layer.

12. The method of claim 1 , wherein the respective copper metal layers within the plurality of contact vias comprise a backend metal layer.

13. A method of forming a device including embedded resistive memory, comprising:
providing a substrate having a plurality of CMOS devices formed thereon;
forming a first copper metal layer over the substrate and comprising a plurality of copper contact pads;
forming a plurality of resistive memory devices over a portion of surface area of the substrate and in contact with respective ones of a corresponding subset of the plurality of copper contact pads within the portion of th

Assignees

• Crossbar Inc

Inventors

• Narayanan Sundar
• Maxwell Steve
• Vasquez Jr Natividad
• Gee Harry Yue

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title