Fabricating memory devices with optimized gate oxide thickness

Patent metadata

Field	Value
Publication number	US-10319727-B2
Application number	US-201715799776-A
Country	US
Kind code	B2
Filing date	Oct 31, 2017
Priority date	Oct 31, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

First claim

What is claimed is:

1. A method comprising:
exposing respective gate areas of programmable memory devices and processor core devices of an integrated-circuit (IC) die and occluding gate areas of input/output (I/O) devices of the IC die;
etching, from the exposed respective gate areas of the programmable memory devices and the processor core devices, a first layer of oxide material;
forming a second layer of oxide material on the IC die, the second layer of oxide material coating the respective gate areas of the programmable memory devices, the processor core devices, and the I/O devices;
exposing the gate areas of the programmable memory devices and occluding the respective gate areas of the processor core devices and the I/O devices;
etching, from the exposed gate areas of the programmable memory devices, the second layer of oxide material; and
forming a third layer of oxide material on the IC die, the third layer of oxide material coating the respective gate areas of the programmable memory devices, the processor core devices, and the I/O devices of the IC die.

2. The method of claim 1 , wherein a thickness of the third layer of oxide material on the gate areas of the programmable memory devices is less than a combined thickness of the second and third layers of oxide material on the gate areas of the processor core devices.

3. The method of claim 1 , wherein the exposing the respective gate areas of the processor core devices and programmable memory devices of the IC die and occluding gate areas of I/O devices of the IC die comprises depositing a photoresist material, radiating light through a lithography mask, and developing the photoresist material.

4. The method of claim 3 , wherein the photoresist material is a positive photoresist material.

5. The method of claim 1 , wherein the forming of the first layer of oxide material, the second layer of oxide material, or the third layer of oxide material forms a layer of silicon oxynitride material, a layer of silicon dioxide material, or a layer of silicon nitride material.

6. The method of claim 1 , wherein the first, the second, or the third layer of oxide material is formed via chemical vapor deposition across the IC die.

7. The method of claim 1 , further comprising forming topographical asperities in the third layer of oxide material at oxide-gate interfaces of the programmable memory devices.

Assignees

• Marvell World Trade Ltd

Inventors

• Chang Runzi
• Lee Winston
• Lee Peter

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title