Vertically integrated nanosheet fuse

Patent metadata

Field	Value
Publication number	US-10319676-B2
Application number	US-201815923009-A
Country	US
Kind code	B2
Filing date	Mar 16, 2018
Priority date	Feb 2, 2017
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a nanosheet stack on a substrate;
modifying a semiconductor layer of the nanosheet stack, wherein modifying the semiconductor layer such that a lateral etch rate of the modified semiconductor layer when exposed to an etchant is greater than a lateral etch rate of unmodified nanosheet layers of the nanosheet stack;
removing portions of the modified semiconductor layer to form a cavity between upper and lower nanosheets, wherein the upper nanosheet is located above the lower nanosheet; and
forming a silicide region in the upper nanosheet.

2. The method of claim 1 , wherein modifying the semiconductor layer comprises implanting a dopant into the semiconductor layer, and wherein the dopant changes an etch rate of the semiconductor layer.

3. The method of claim 2 , wherein the modified semiconductor layer comprises silicon germanium (SiGe), the upper and lower nanosheets comprise silicon (Si), and the dopant comprises Si or germanium (Ge).

4. The method of claim 3 , wherein a concentration of Ge in the modified semiconductor layer is about 10 percent and a break down voltage of the modified semiconductor layer is about 2.9V.

5. The method of claim 3 , wherein a concentration of Ge in the modified semiconductor layer is about 20 percent and a break down voltage of the modified semiconductor layer is about 2.8V.

6. The method of claim 3 , wherein a concentration of Ge in the modified semiconductor layer is about 30 percent and a break down voltage of the modified semiconductor layer is about 2.5V.

7. The method of claim 1 , wherein modifying the semiconductor layer comprises epitaxially growing the semiconductor layer from a material comprising a greater etch rate with respect to an etchant than an etch rate of the upper and lower nanosheets when exposed to the etchant.

8. The method of claim 1 , wherein forming the silicide region in the upper nanosheet comprises:
forming a conformal liner over the nanosheet stack and the substrate; and
annealing the conformal liner and the nanosheet stack at a temperature of greater than about 100 degrees Celsius.

9. The method of claim 8 , wherein the conformal liner comprises nickel (Ni), titanium (Ti), or platinum (Pt).

10. The method of claim 1 further comprising forming a spacer over the nanosheet stack, wherein portions of the spacer fill the cavity.

11. The method of claim 10 further comprising forming a dielectric region over the nanosheet stack, the spacer, and the substrate.

12. The method of claim 11 further comprising forming a conductive contact in the dielectric region and on the silicide region in the upper nanosheet.

13. A method for forming a semiconductor device, the method comprising:
forming a plurality of nanosheet stacks on a substrate;
modifying a semiconductor layer of the plurality of nanosheet stacks, wherein modifying the semiconductor layer such that a lateral etch rate of the modified semiconductor layer when exposed to an etchant is greater than a lateral etch rate of unmodified nanosheet layers of the nanosheet stack;
removing portions of the modified semiconductor layer to form a cavity between an upper and lower nanosheets of each nanosheet stack; and
forming a silicide region in the upper nanosheet of each nanosheet stack.

14. The method of claim 13 , wherein modifying the semiconductor layers comprises implanting a dopant into the semiconductor layers, and wherein the dopant increases an etch rate of the semiconductor layers.

15. The method of claim 14 , wherein each semiconductor layer comprises silicon germanium (SiGe), each upper and lower nanosheet comprises silicon (Si), and the dopant comprises Si or germanium (Ge).

16. The method of claim 15 , wherein a concentration of Ge in the modified semiconductor layer is about 10 percent and a break down voltage of the modified semiconductor layer is about 2.9V.

17. A semiconductor device comprising:
a nanosheet stack formed on a substrate, the nanosheet stack comprising a modified semiconductor layer formed on a nanosheet, wherein the modified semiconductor layer comprises a lateral etch rate of the modified semiconductor layer when exposed to an etchant is greater than a lateral etch rate of other unmodified nanosheet layers of the nanosheet stack;
a silicide layer formed on the substrate and adjacent to the nanosheet stack;
a first conductive contact formed on a silicide region; and
a second conductive contact formed on a surface of the silicide layer.

18. The semiconductor device of claim 17 , wherein the nanosheet comprises a thickness of about 4 nanometers to about 10 nanometers, and wherein the modified semiconductor layer comprises a thickness of about 6 nanometers to about 20 nanometers.

19. The semiconductor device of claim 17 , wherein a concentration of Ge in the modified semiconductor layer is about 20 percent and a break down voltage of the modified semiconductor layer is about 2.8V.

20. The semiconductor device of claim 17 , wherein a concentration of Ge in the modified semiconductor layer is about 30 percent and a break down voltage of the modified semiconductor layer is about 2.5V.

Assignees

• IBM

Inventors

• Chao Robin H
• Demarest James J
• Loubet Nicolas J

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/493 Primary

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title