Semiconductor package with elastic coupler and related methods

Patent metadata

Field	Value
Publication number	US-10319652-B2
Application number	US-201715630112-A
Country	US
Kind code	B2
Filing date	Jun 22, 2017
Priority date	Feb 19, 2015
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a die coupled to a substrate;
a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and;
a pin fixedly coupled to the housing and electrically coupled with the die, the pin comprising a reversibly elastically deformable lower portion, the reversibly elastically deformable lower portion coupled with a lower end of the pin;
wherein the reversibly elastically deformable lower portion is located in the pin between the housing and the substrate; and
wherein the reversibly elastically deformable lower portion is configured to compress to prevent the lower end of the pin from lowering beyond a predetermined point relative to the lower end of the pin when the housing is lowered to be coupled to the substrate.

2. The semiconductor package of claim 1 , wherein a base of the pin is coupled to the substrate with a spring.

3. The semiconductor package of claim 1 , wherein the pin is fixedly coupled in a top of the housing and is configured to be coupled with the substrate by lowering the housing towards the substrate.

4. The semiconductor package of claim 1 , wherein the reversibly elastically deformable lower portion comprises a spring.

5. A semiconductor package, comprising:
at least one die coupled to a substrate;
a housing coupled to the substrate and at least partially enclosing the at least one die within a cavity of the housing, and;
a plurality of pins fixedly coupled in a top of the housing, each of the plurality of pins electrically coupled with one of the at least one die through a connection trace of the substrate, each of the plurality of pins comprising a spring between an upper portion of the pin and a lower portion of the pin;
wherein the spring of each pin biases an upper portion of the pin towards the housing; and
wherein the spring is located in the pin between the housing and the substrate.

6. The semiconductor package of claim 5 , wherein the spring comprises a coil spring.

7. The semiconductor package of claim 5 , wherein the spring of each pin is compressed along a direction substantially parallel with a longest length of the pin.

8. The semiconductor package of claim 5 , wherein the spring of each pin is configured to prevent a contact surface of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered towards the substrate.

9. The semiconductor package of claim 5 , wherein the spring is a helical spring.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Lin Yusheng
• Chew Chee Hiong
• Carney Francis J

Classifications

• H01R4/489

  spring force increased by screw, cam, wedge, or other fastening means · CPC title

• H01R4/4863

  Coil spring · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title