Signal conversion device, processing device, communication system, and signal conversion method

Patent metadata

Field	Value
Publication number	US-10319407-B2
Application number	US-201815943086-A
Country	US
Kind code	B2
Filing date	Apr 2, 2018
Priority date	Jul 1, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A signal conversion device includes a first converting section configured to convert a clock signal input through a first signal line, a data signal input through a second signal line, and a control signal input through a third signal line, into pulse signals including a first pulse train and a second pulse train; and a transmitting section configured to transmit the first pulse train through a fourth signal line and the second pulse train through a fifth signal line, wherein the control signal is a signal that, through a level transition, causes a control target device to switch between an active state and an inactive state, and wherein the first converting section is configured to put successive pulses into at least one of the first pulse train and the second pulse train in response to the level transition of the control signal.

First claim

What is claimed is:

1. A signal conversion device comprising:
a first converting section configured to convert a clock signal input through a first signal line, a data signal input through a second signal line, and a control signal input through a third signal line, into a first pulse train and a second pulse train; and
a transmitting section configured to transmit the first pulse train through a fourth signal line and the second pulse train through a fifth signal line.

2. The signal conversion device of claim 1 , wherein the first converting section is configured to put pulses into the first pulse train and the second pulse train based on a level of the data signal at a timing of a level transition in the clock signal.

3. The signal conversion device of claim 2 , wherein the first converting section:
puts one pulse into the first pulse train and then puts one pulse into the second pulse train in a case in which the data signal is at a high level at a timing of a rising level transition in the clock signal, and
puts one pulse into the second pulse train and then puts one pulse into the first pulse train in a case in which the data signal is at a low level at the timing of the rising level transition in the clock signal.

4. The signal conversion device of claim 2 , wherein:
the control signal is a signal that, through a level transition, causes a control target device to switch between an active state and an inactive state, and
the first converting section is configured to put successive pulses into at least one of the first pulse train or the second pulse train in response to the level transition of the control signal.

5. The signal conversion device of claim 4 , wherein:
the first converting section is configured to put successive pulses into one of the first pulse train or the second pulse train in response to a rising level transition of the control signal; and
the first converting section is configured put successive pulses into an other of the first pulse train or the second pulse train in response to a falling level transition of the control signal.

6. The signal conversion device of claim 4 , wherein the first converting section is configured to put first successive pulses into one of the first pulse train or the second pulse train in response to the level transition of the control signal, and after the first successive pulses, the first converting section puts second successive pulses into an other of the first pulse train or the second pulse train.

7. The signal conversion device of claim 4 , wherein a pulse width of the pulses put into the first pulse train and the second pulse train based on the level of the data signal at a timing of a level transition in the clock signal and a pulse width of each pulse of the successive pulses are the same.

8. The signal conversion device of claim 4 , wherein the first pulse train and the second pulse train include designation information that designates one of a plurality of the control target devices.

9. A processing device comprising:
a receiving section configured to receive the first pulse train and the second pulse train transmitted from the signal conversion device of claim 1 ;
a second converting section configured to convert the first pulse train and the second pulse train to the clock signal, the data signal, and the control signal; and
a processing section configured to perform predetermined processing based on the clock signal, the data signal, and the control signal.

10. The processing device of claim 9 , further comprising a transmitting section configured to transmit the first pulse train and the second pulse train received by the receiving section.

11. The processing device of claim 10 , wherein, in a case in which a command included in the data signal is to read data, the second converting section converts data obtained by the predetermined processing of the processing section into the first pulse train and the second pulse train, and transmits via the transmitting section.

12. The processing device of claim 9 , wherein the processing section measures a cell voltage of a battery cell as the predetermined processing.

13. A signal conversion method comprising:
converting a clock signal input through a first signal line, a data signal input through a second signal line, and a control signal input through a third signal line into a first pulse train and a second pulse train.

14. The signal conversion method of claim 13 , wherein the conversion is performed by putting pulses into the first pulse train and the second pulse train based on a level of the data signal at a timing of a level transition in the clock signal.

15. The signal conversion method of claim 13 , wherein:
the control signal is a signal that, through a level transition, causes a control target device to switch between an active state and an inactive state; and
successive pulses are put into at least one of the first pulse train or the second pulse train in response to the level transition of the control signal.

Assignees

• Lapis Semiconductor Co Ltd

Inventors

• Kita Yukihiro

Classifications

• H04B3/141 Primary

  using multiequalisers, e.g. bump, cosine, Bode · CPC title

• H04L25/0278

  Arrangements for impedance matching · CPC title

• G11B15/1875

  adaptations for special effects or editing (signal processing or indexing therefor G11B27/00) · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• G11B27/3027

  used signal is digitally coded · CPC title