Computer system for performing adaptive interrupt control and method for controlling interrupt thereof

Patent metadata

Field	Value
Publication number	US-10318174-B2
Application number	US-201715598850-A
Country	US
Kind code	B2
Filing date	May 18, 2017
Priority date	May 19, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.

First claim

What is claimed is:

1. A computer system comprising:
a storage device configured to receive an input/output (IO) request, and to send an interrupt after completing the IO request, the interrupt indicating that an IO associated with the IO request is an IO completion; and
a host configured to,
generate the IO request,
tally a number of the IO request sent by the host, and a number of the IO completion by the storage device,
determine a number of delayed IOs based on the number of the IO request and the number of the IO completion,
calculate an interrupt control level based on the number of delayed IOs, and
selectively adjust a frequency of the interrupt from the storage device in response to the interrupt control level being greater than a threshold, wherein
the host is configured to selectively transmit an interrupt control command to the storage device in response to the host determining that the interrupt control level is greater than the threshold, and
the storage device is configured to adjust the frequency of the interrupt based on the interrupt control command.

2. The computer system as set forth in claim 1 , wherein the host comprises:
a memory including,
a submission queue configured to store the number of the IO request generated by the host, and
a completion queue configured to store the number of the IO completion completed by the storage device.

3. The computer system as set forth in claim 2 , wherein the host is configured to calculate the number of the delayed IOs as a sum of the number of IO requests stored in the submission queue and the number of IO completions stored in the completion queue.

4. The computer system as set forth in claim 2 , wherein the host is configured to calculate the number of the delayed IOs as a difference between the number of IO requests stored in the submission queue and the number of IO completions stored in the completion queue.

5. The computer system as set forth in claim 1 , wherein the host is configured to,
monitor a load status of a central processing unit, and
selective adjust the frequency of the interrupt from the storage device based on the load status and the number of the delayed IOs.

6. The computer system as set forth in claim 5 , wherein the host is configured to activate an adaptive interrupt control of the storage device based on an idle ratio of the central processing unit and a threshold.

7. The computer system as set forth in claim 5 , wherein the host is configured to adjust the frequency of the interrupt by,
selectively sending the interrupt control command to the storage device based on the interrupt control level.

8. The computer system as set forth in claim 7 , wherein the host is configured to determine a load status of the central processing unit.

9. The computer system as set forth in claim 8 , wherein the host is configured to execute a device driver to drive the storage device.

10. A computer system comprising:
a first storage device configured to receive a first input/output (IO) request, and to send a first interrupt after completing the first IO request, the first interrupt indicating that a first IO associated with the first IO request is a first IO completion;
a second storage device configured to receive a second IO request, and to send a second interrupt after completing the second IO request, the second interrupt indicating that a second IO associated with the second IO request is a second IO completion; and
a host including a first processor and a second processor, the host configured to,
perform adaptive interrupt control of the first processor by,
tallying a number of the first IO request sent by the host, and a number of the first IO completion by the first storage device,
determining a number of delayed first IOs based on the number of the first IO request and the number of the first IO completion,
calculating a first interrupt control level based on the number of delayed first IOs, and
selectively adjusting a frequency of the first interrupt from the first storage device in response to the first interrupt control level being greater than a first threshold, and

perform adaptive interrupt control of the second processor by,
tallying a number of the second IO request sent by the host, and a number of the second IO completion by the second storage device,
determining a number of delayed second IOs based on the number of the second IO request and the number of the second IO completion,
calculating a second interrupt control level based on the number of delayed second IOs, and
selectively adjusting a frequency of the second interrupt of the second storage device in response to the second interrupt control level being greater than a second threshold, wherein
each of the first processor and the second processor is configured to selectively send an interrupt control command to the first and second storage devices based on the first interrupt control level and the second interrupt control level respectively.

11. The computer system as set forth in claim 10 , wherein the host is further configured to monitor a load status of the first processor and the second processor.

12. The computer system as set forth in claim 11 , wherein the host is configured to,
activate the adaptive interrupt control of the first storage device based on an idle state of the first processor and the first threshold, and
activate the adaptive interrupt control of the second storage device based on an idle state of the second processor and the second threshold.

13. A host device comprising:
an interface configured to communicate with a storage device; and
a processor configured to selectively activate adaptive interrupt control (AIC) based on one or more of an idle ratio associated with the host device and a number of delayed interrupts (IOs), the processor configured to selectively activate the AIC by,
tallying a number of IO requests sent by the host device, and a number of IOs completed by the storage device,
determining the number of delayed IOs based on the number of IO requests and the number of IOs completed,
calculating an interrupt control level (ICL) based on at least the number of delayed IOs, and
selectively instructing the storage device to perform the AIC, if the ICL is greater than a threshold, the interrupt control command instructing the storage device to reduce a number of interrupts transmitted to the host device, wherein the processor is configured to,
determine an idle ratio associated with the host device based on a load status of the processor, and
calculate the ICL based on the idle ratio and the number of delayed IOs.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-San
• Kim Kyung Ho
• Kim Seokhwan
• Shin Seunguk
• Lim Jihyun

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F2209/548

  Queue · CPC title