System on chip, method of managing power thereof, and electronic device

US10317984B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10317984-B2
Application numberUS-201514983809-A
CountryUS
Kind codeB2
Filing dateDec 30, 2015
Priority dateJan 23, 2015
Publication dateJun 11, 2019
Grant dateJun 11, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system on chip includes an event manager configured to receive an event from an external source, an event analyzer configured to analyze the event received by the event manager to determine a voltage, a frequency, and power gating corresponding to the analyzed event, a power manager configured to set power on or off and to set a voltage, a clock manager configured to set a clock frequency, a power gating (PG) manager configured to set power gating, a main controller configured to include at least one modules and a central processing unit (CPU), and a wakeup controller configured to control the power manager, the clock manager, and the PG manager, to transmit power having a starting voltage and a clock signal having a starting clock frequency, and to transmit a power gating signal to apply power only to one of the at least one modules operating so as to start the main controller.

First claim

Opening claim text (preview).

What is claimed is: 1. A system on chip (SoC) powered by a power supply unit, comprising: an event manager configured to receive an event from an external source; an event analyzer configured to analyze the event received by the event manager to identify a voltage, a frequency, and power gating corresponding to the analyzed event; a power manager configured to set power on or off, and to set a starting voltage; a clock manager configured to set a starting clock frequency; a power gating (PG) manager configured to set a power gating; a main controller comprising at least one module and a central processing unit (CPU); and a wakeup controller configured to control the power manager to set the starting voltage to the identified voltage, to control the clock manager to set the starting clock frequency to the identified frequency, to control the PG manager to set the power gating to the identified power gating, to transmit a clock signal having the starting clock frequency to the main controller, to transmit a control signal to the power supply unit, the control signal being configured to control the power supply unit to supply power having the starting voltage to the main controller, and to start the main controller by transmitting a power gating signal corresponding to the identified power gating to the main controller, wherein a module corresponding to the event from among the at least one module, is powered by the power supply unit, based on the power gating signal, and wherein the wakeup controller is configured to identify whether the power supplied to the main controller is stabilized with the starting voltage and, in response to identifying that the power is stabilized with the starting voltage, transmit the clock signal having the starting clock frequency to the main controller. 2. The SoC of claim 1 , further comprising: a parameter storage unit configured to store preset information, wherein the event analyzer is configured to analyze the event by using the preset information stored in the parameter storage unit. 3. The SoC of claim 2 , wherein the preset information comprises at least one selected from a minimum voltage, a minimum frequency, and power gating for performing an operation corresponding to each event. 4. The SoC of claim 1 , wherein the event is at least one selected from a timer event, a sensor event, a communication connection event, and a message event. 5. The SoC of claim 1 , wherein the main controller executes an operating system (OS) of the SoC by using the transmitted power and clock signal. 6. A method of managing power of a system on chip (SoC), the method comprising: in response to an event being input from an external source, analyzing the input event to identify a voltage, a frequency, and power gating corresponding to the analyzed event; setting a starting voltage to the identified voltage; setting a starting clock frequency to the identified frequency; setting a power gating to the identified power gating; and starting a main controller by transmitting a control signal to a power supply unit, the control signal being configured to control the power supply unit to supply power having the starting voltage to the main controller; identifying whether the power supplied to the main controller is stabilized with the starting voltage; and transmitting a clock signal having the starting clock frequency, and a power gating signal corresponding to the set power gating to the main controller, wherein the starting the main controller comprises supplying power to a module being required for the event from among a plurality of modules included in the main controller, based on the power gating signal, and wherein the transmitting the clock signal comprises in response to identifying that the power is stabilized with the starting voltage, transmitting the clock signal having the starting clock frequency to the main controller. 7. The method of claim 6 , further comprising: storing preset information, wherein the analyzing the input event to determine the voltage, the frequency, and the power gating comprises analyzing the input event by using the stored preset information. 8. The method of claim 7 , wherein the event is at least one selected from a timer event, a sensor event, a communication connection event, and a message event. 9. The method of claim 7 , wherein the preset information comprises at least one selected from a minimum voltage, a minimum frequency, and power gating necessary for performing an operation corresponding to the input event. 10. The method of claim 6 , wherein the starting of the main controller further comprises executing an OS of the SoC through the main controller by using the supplied power and the transmitted clock signal. 11. An electronic device comprising: a power supply unit; a system on chip (SoC), the SoC being configured to control the electronic device and comprising: an event manager configured to receive an event from an external source; an event analyzer configured to analyze the event received by the event manager to identify a voltage, a frequency, and power gating corresponding to the analyzed event; a power manager configured to set power on or off and to set a starting voltage; a clock manager configured to set a starting clock frequency; a power gating (PG) manager configured to set a power gating; a main controller configured to comprise at least one module and a CPU; and a wakeup controller configured to control the power manager to set the starting voltage to the identified voltage, to control the clock manager to set the starting clock frequency to the identified frequency, to control the PG manager to set the power gating to the identified power gating, to transmit a clock signal having the starting clock frequency to the main controller, transmit a control signal to the power supply unit, the control signal being configured to control the power supply unit to supply power having the starting voltage to the main controller, and start the main controller by transmitting a power gating signal corresponding to the set power gating to the main controller, wherein a module corresponding to the event from among the at least one module, is powered by the power supply unit, based on the power gating signal, and wherein the wakeup controller is configured to identify whether the power supplied to the main controller is stabilized with the starting voltage and, in response to identifying that the power is stabilized with the starting voltage, transmit the clock signal having the starting clock frequency to the main controller. 12. A method of managing power, comprising: receiving a task request corresponding to a task, the task corresponding to a task voltage, a task clock frequency, a task clock gating, and a task power gating; identifying, by a low power controller, the task voltage, the task clock frequency, the task clock gating, and the task power gating corresponding to the task; waking, by the low power controller, a main controller from a system sleep state, the waking comprising: transmitting a control signal to a power supply unit, the control signal being configured to control the power supply unit to supply power having the task voltage to the main controller; transmitting a clock signal having the task clock frequency to the main controller; transmitting a clock gating signal corresponding to the task clock gating to the main controller; transmitting a power gating signal corresponding to the task power gating to the main controller; and supplying power to a module being required for performing the task from among a plurality of modules included in the

Assignees

Inventors

Classifications

  • G06F1/329Primary

    by task scheduling · CPC title

  • Power saving characterised by the action undertaken · CPC title

  • by lowering the supply or operating voltage · CPC title

  • G06F1/3243Primary

    Power saving in microcontroller unit · CPC title

  • by switching off individual functional units in the computer system · CPC title

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Frequently asked questions

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What does patent US10317984B2 cover?
A system on chip includes an event manager configured to receive an event from an external source, an event analyzer configured to analyze the event received by the event manager to determine a voltage, a frequency, and power gating corresponding to the analyzed event, a power manager configured to set power on or off and to set a voltage, a clock manager configured to set a clock frequency, a …
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F1/329. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 11 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).