Peripheral device expansion card system

US10317973B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10317973-B2
Application numberUS-201715677828-A
CountryUS
Kind codeB2
Filing dateAug 15, 2017
Priority dateAug 15, 2017
Publication dateJun 11, 2019
Grant dateJun 11, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A computing system includes a system board having a system controller device with an interrupt input. A system expansion bus connector is located on the system board and includes power pin(s) and an interrupt signal pin connected to the interrupt input. A peripheral device expansion card system is coupled to the computing system through system expansion bus connector and includes a system power reporting device coupled to the power pin(s) to receive power from the computing system via the power pin(s), and a card controller device coupled to the system power reporting device and to the interrupt signal pin. The card controller device determines, using the system power reporting device, a power state of the computing system. The card controller device also sends, to the system controller device through the interrupt signal pin, an interrupt signal that the system controller device interprets as a hot plug event.

First claim

Opening claim text (preview).

What is claimed is: 1. An Information Handling System (IHS), comprising: a computing system that includes a system board having: a system controller device including an interrupt input; and an system expansion bus connector that is located on the system board and that includes: at least one power pin; and an interrupt signal pin that is connected to the interrupt input; and a peripheral device expansion card system that is coupled to the computing system through system expansion bus connector and that includes: a system power reporting device that is coupled to the at least one power pin and configured to receive power from the computing system via the at least one power pin; and a card controller device that is coupled to the system power reporting device and to the interrupt signal pin, wherein the card controller device is configured to: determine, using the system power reporting device, a power state of the computing system; and send, to the system controller device through the interrupt signal pin, a interrupt signal, wherein the system controller device is configured to interpret the interrupt signal as a hot plug event. 2. The IHS of claim 1 , wherein the peripheral expansion card system includes: a power activation device that is coupled to the card controller device and that is configured to be activated to cause the card controller device to remain powered when the peripheral device expansion card system is decoupled from the computing system. 3. The IHS of claim 1 , wherein system power reporting device includes a voltage divider device that is configured to receive a first power amount through the at least one power pin and provide a second power amount that is less than the first power amount to the card controller device, and wherein the card controller device determines the power state of the computing system using the second power amount. 4. The IHS of claim 1 , wherein the interrupt signal pin is provided by a previously reserved pin on the system expansion bus connector that is utilized by the card controller device to transmit interrupt signals. 5. The IHS of claim 1 , wherein card controller device is configured to determine a powered off power state of the computing system using the system power reporting device, and wherein the system expansion bus connector includes: a power sleep state signal pin that is coupled to the system controller device and the card controller device, wherein the system controller device is configured to report a power sleep state of the computing system through the power sleep state signal pin to the card controller device. 6. The IHS of claim 5 , wherein power sleep state signal pin is provided by a previously reserved pin on the system expansion bus connector that is utilized by the system controller device to transmit power sleep state signals. 7. A peripheral device expansion card system, comprising: a card base; a card expansion bus connector that is located on the card base, that is configured to couple to a system board, and that includes: at least one power pin; and an interrupt signal pin; a system power reporting device that is located on the card base, coupled to the at least one power pin, and configured to receive power via the at least one power pin; and a card controller device that is coupled to the system power reporting device and to the interrupt signal pin, wherein the card controller device is configured to: determine, using the system power reporting device, a power state of a computing system that includes the system board; and send, through the interrupt signal pin, a interrupt signal that is configured to signify a hot plug event. 8. The system of claim 7 , further comprising: a power activation device that is located on the card base, coupled to the card controller device, and configured to be activated to cause the card controller device to remain powered when the card expansion bus connector is decoupled from the system board. 9. The system of claim 7 , wherein system power reporting device includes a voltage divider device that is configured to receive a first power amount through the at least one power pin and provide a second power amount that is less than the first power amount to the card controller device, and wherein the card controller device determines the power state of the computing system using the second power amount. 10. The system of claim 7 , wherein the interrupt signal pin is provided by a previously reserved pin on the card expansion bus connector that is utilized by the card controller device to transmit interrupt signals. 11. The system of claim 7 , wherein card controller device is configured to determine a powered off power state of the computing system using the system power reporting device, and wherein the card expansion bus connector includes: a power sleep state signal pin that is coupled to the card controller device, wherein the card controller device is configured to receive a power sleep state of the computing system through the power sleep state signal pin from the computing system. 12. The system of claim 11 , wherein power sleep state signal pin is provided by a previously reserved pin on the system expansion bus connector that is utilized by the computing system to transmit power sleep state signals. 13. The system of claim 7 , further comprising: a multiplexer that is located on the card base and coupled between the system power reporting device and the card controller device, wherein the multiplexer is configured to receive a first multiplexer input from the system power reporting device and, in response, provide a first multiplexer output to the card controller device for use in determining the power state of the computing device; a de-multiplexer that is located on the card base and coupled between the card controller device and the interrupt signal pin, wherein the de-multiplexer is configured to receive a first de-multiplexer input from the card controller device and, in response, provide the interrupt signal pin a first de-multiplexer output that includes the interrupt signal that is configured to signify the hot plug event; a sideband cable connector located on the card base; a power state pin that is located on the sideband cable connector and that is coupled to the multiplexer, wherein the multiplexer is configured to receive a second multiplexer input from the power state pin and provide the first multiplexer output to the card controller device for use in determining the power state of the computing device; and a hot plug event signal pin that is located on the sideband cable connector and that is coupled to the de-multiplexer, wherein the de-multiplexer is configured to receive the first de-multiplexer input from the card controller device and provide a second de-multiplexer output that is configured to signify the hot plug event. 14. A method for providing a peripheral device expansion card system with a computing system, comprising: providing, in response to the connection of a card expansion bus connector that is located on a peripheral device expansion card system and a system expansion bus connector that is located on a computing system, at least one power connection and an interrupt signal connection; receiving, by a system power reporting device that is located on the peripheral device expansion card system and coupled to the at least one power connection, power from the computing system via the at least one power connection; determining, by a card controller device that is located on the peripheral device expansion card system and using the system power reporting de

Assignees

Inventors

Classifications

  • Program control for peripheral devices (G06F13/14 - G06F13/42 take precedence) · CPC title

  • using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

  • Power saving in PCMCIA card · CPC title

  • by switching off individual functional units in the computer system · CPC title

  • G06F1/266Primary

    Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

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Frequently asked questions

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What does patent US10317973B2 cover?
A computing system includes a system board having a system controller device with an interrupt input. A system expansion bus connector is located on the system board and includes power pin(s) and an interrupt signal pin connected to the interrupt input. A peripheral device expansion card system is coupled to the computing system through system expansion bus connector and includes a system power…
Who is the assignee on this patent?
Dell Products Lp
What technology area does this patent fall under?
Primary CPC classification G06F1/266. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 11 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).