Finite impulse response analog receive filter with amplifier-based delay chain

Patent metadata

Field	Value
Publication number	US-10313165-B2
Application number	US-201715453774-A
Country	US
Kind code	B2
Filing date	Mar 8, 2017
Priority date	Mar 8, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.

First claim

What is claimed is:

1. A channel interface module comprising:
multiple amplifier-based delay circuits arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal, each amplifier-based delay circuit in the sequential chain including one or more delay cells each employing a cascode amplifier with a source follower output stage to introduce additional delay to the analog input signal, the cascode amplifier within each delay cell having:
a MOS (metal-oxide-semiconductor) transistor with a gate that receives a delay cell input signal; and
a gate-to-drain capacitance in excess of an intrinsic value for the MOS transistor;
a symbol decision circuit operating on the equalized signal to obtain a sequence of symbol decisions; and
an interface that extracts received data from the sequence of symbol decisions.

2. The module of claim 1 , wherein the gate-to-drain capacitance is at least 2 femtofarads (fF) and no more than 10 fF.

3. The module of claim 2 , wherein the gate-to-drain capacitance is provided by routing a conductor to the gate in close proximity to a drain of the MOS transistor or a conductor connected to said drain.

4. A channel interface module comprising:
multiple amplifier-based delay circuits arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal, each amplifier-based delay circuit in the sequential chain including a sequence of multiple delay cells each employing a cascode transistor for a common source amplifier and a source follower stage including a transistor configured to provide a source follower output to introduce additional delay to the analog input signal;
a symbol decision circuit operating on the equalized signal to obtain a sequence of symbol decisions: and
an interface that extracts received data from the sequence of symbol decisions.

5. A channel interface module comprising:
multiple amplifier-based delay circuits arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal, each amplifier-based delay circuit including one or more delay cells each employing a differential common source amplifier with adjustable source degeneration to introduce additional delay to the analog input signal;
wherein the differential common source amplifier within each delay cell comprises:
a pair of MOS transistors with gates that receive a differential input signal to the delay cell and drains that each are coupled to the respective gate by a gate-to-drain capacitance in excess of an intrinsic value for the MOS transistors;

a symbol decision circuit operating on the equalized signal to obtain a sequence of symbol decisions; and
an interface that extracts received data from the sequence of symbol decisions.

6. The module of claim 5 , wherein each of the one or more delay cells further includes:
cascode transistors for the differential common source amplifier; and
a source-follower including transistors configured to drive differential output signals from that delay cell.

7. The module of claim 6 , wherein each of the one or more delay cells further includes:
adjustable current sources coupled to the cascode transistors to set a common mode voltage of the differential output signals to bias a subsequent delay cell without series capacitive coupling.

8. The module of claim 6 , further comprising an arrangement of amplifier-based summer circuits that weight and combine together the set of increasingly-delayed analog signals together with the analog input signal to form equalized signals, wherein each amplifier-based summer circuit comprises:
a first differential common source amplifier for a first of two input signals;
a second differential common source amplifier for a second of the two input signals, the first and second differential common source amplifiers additively combining currents through a cascode transistor stage, each of the two differential common source amplifiers having adjustable source degeneration for independent gain control; and
a source-follower stage that drives differential output signals from the amplifier-based summer circuit.

9. A method for providing high speed equalization, the method comprising:
obtaining an analog receive signal from a communications channel;
using a chain of amplifier-based delay circuits to convert the analog receive signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog received signal to form an equalized signal, each of said amplifier-based delay circuits having one or more delay cells, each of said one or more delay cells:
receiving a delay cell input signal with a gate of a MOS transistor in a cascode amplifier configuration, said receiving including coupling the input signal from the gate to a drain of the MOS transistor with a gate-to-drain capacitance in excess of an intrinsic value for the MOS transistor, and
buffering an output of that delay cell with a source follower output stage;

sampling the equalized signal to obtain a sequence of symbol decisions; and
extracting received data from the sequence of symbol decisions.

10. A method for providing high speed equalization, the method comprising:
obtaining an analog receive signal from a communications channel, the analog receive signal being a differential signal;
using a chain of amplifier-based delay circuits to convert the analog receive signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog received signal to form an equalized signal, each amplifier-based delay circuit accepting a differential input signal with a differential cascade amplifier stage including cascade transistors and providing a differential output signal by a source follower stage including transistors with an output buffer stage;
sampling the equalized signal to obtain a sequence of symbol decisions; and
extracting received data from the sequence of symbol decisions.

11. The method of claim 10 , wherein each of said amplifier-based delay circuits comprises one or more delay cells, and wherein said using a chain of amplifier-based delay circuits includes, for each delay cell:
receiving a differential delay cell input signal with gates of two MOS transistors in a differential common source amplifier configuration; and
buffering a differential output of that delay cell with a source-follower including transistors configured to drive differential output signals.

12. The method of claim 11 , wherein said receiving includes coupling each gate to a respective drain of the MOS transistors with a gate-to-drain capacitance in excess of an intrinsic value for that MOS transistor.

13. The method of claim 12 , wherein each gate-to-drain capacitance is provided by a routing gate conductor in close proximity to a respective drain or in close proximity to a conductor connected to said respective drain.

Assignees

• Credo Tech Group Ltd

Inventors

• Cheng Lawrence Chi Fung
• Luo Haihui

Classifications

• H04L27/01 Primary

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03F3/45201

  Non-folded cascode stages · CPC title

• H03G5/28

  having semiconductor devices · CPC title

• H03F2203/45361

  the AAC comprising multiple transistors parallel coupled at their drains only, e.g. in a cascode dif amp, only those forming the composite common source transistor · CPC title