Apparatus and method for multiplexing multi-lane multi-mode data transport

Patent metadata

Field	Value
Publication number	US-10313157-B2
Application number	US-201715646147-A
Country	US
Kind code	B2
Filing date	Jul 11, 2017
Priority date	Apr 25, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a logical signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a pin of a multi-lane, multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad, wherein the external processor is configured to process an electrical signal at the second port in accordance with a first protocol when the logical signal is asserted, and the internal processor is configured to process an electrical signal at the first I/O pad in accordance with a second protocol when the logical signal is de-asserted.

First claim

What is claimed is:

1. An apparatus comprising:
a semiconductor die including:
a first I/O (input/output) pad, a second I/O pad, and a third I/O pad;
a first internal processor configured to process an electrical signal at the first I/O pad in accordance with a first protocol, when a first logical signal is de-asserted,
a second internal processor configured to process an electrical signal at the second I/O pad in accordance with the first protocol, when a second logical signal is de-asserted,
a first switch configured to electrically connect the first I/O pad to the third I/O pad, when the first logical signal is asserted, and
a second switch configured to electrically connect the second I/O pad to the third I/O pad when the second logical signal is asserted; and

a semiconductor package including:
a first bond pad configured to electrically connect to the first I/O pad,
a second bond pad configured to electrically connect to the second I/O pad,
a third bond pad configured to electrically connect to the third I/O pad,
a first port configured to electrically connect to a first pin of a multi-lane, multi-mode connector,
a second port configured to electrically connect to a second pin of the multi-lane, multi-mode connector, and
a third port configured to electrically connect to an external processor configured to process an electrical signal at the third port in accordance with a second protocol, wherein the first port is electrically connected to the first bond pad via a first routing path, the second port is electrically connected to the second bond pad via a second routing path, and the third port is electrically connected to the third bond pad via a third routing path.

2. The apparatus of claim 1 , wherein the first bond pad electrically connects to the first I/O pad via a first bond wire, the second bond pad electrically connects to the second I/O pad via a second bond wire, and the third bond pad electrically connects to the third I/O pad via a first bond wire.

3. The apparatus of claim 1 , wherein the semiconductor package is a BGA (ball grid array) package.

4. The apparatus of claim 1 , wherein the first port electrically connects to the first pin of the multi-lane, multi-mode connector via a first metal trace laid out on a PCB (printed circuit board), while the third port electrically connects to the external processor via a second metal trace laid out on the PCB.

5. The apparatus of claim 1 , wherein the second protocol is a USB (universal serial bus) protocol, while the first protocol is a DisplayPort protocol.

6. The apparatus of claim 2 , wherein the first bond wire and the third bond wire are substantially parallel and adjacent to each other.

7. The apparatus of claim 2 , wherein the second bond wire and the third bond wire are substantially parallel and adjacent to each other.

8. The apparatus of claim 3 , wherein the first routing path includes a metal trace.

9. The apparatus of claim 3 , wherein the third routing path includes a via.

10. The apparatus of claim 4 , wherein the first metal trace and the second metal trace are laid out on different layers of the PCB.

11. The apparatus of claim 8 , wherein the first routing path further includes a via.

12. A method comprising:
electrically connecting a first port, a second port, and a third port of a semiconductor package to a first pin of a multi-lane, multi-mode connector, a second pin of the multi-lane, multi-mode connector, and an external processor, respectively, wherein the external processor is configured to process an electrical signal associated with the third port in accordance with a first protocol;
electrically connecting the first port, the second port, and the third port to a first bond pad, a second bond pad, and a third bond pad of the semiconductor package, respectively;
electrically connecting the first bond pad, the second bond pad, and the third bond pad to a first I/O pad, a second I/O pad, and a third I/O pad of a semiconductor die, respectively;
electrically connecting the first I/O pad with the third I/O pad using a first switch in response to a first logical signal being asserted, else processing an electrical signal at the first I/O pad using a first internal processor in accordance with a second protocol; and
electrically connecting the second I/O pad with the third I/O pad using a second switch in response to a second logical signal being asserted, else processing an electrical signal at the second I/O pad using a second internal processor in accordance with the second protocol.

13. The method of claim 12 , wherein the first bond pad electrically connects to the first I/O pad via a first bond wire, the second bond pad electrically connects to the second I/O pad via a second bond wire, and the third bond pad electrically connects to the third I/O pad via a third bond wire.

14. The method of claim 12 , wherein the semiconductor package is a BGA (ball grid array) package.

15. The method of claim 12 , wherein the first port electrically connects to the first pin of the multi-lane, multi-mode connector via a first metal trace laid out on a PCB (printed circuit board), while the third port electrically connects to the external processor via a second metal trace laid out on the PCB.

16. The method of claim 12 , wherein the first protocol is a USB (universal serial bus) protocol, while the second protocol is a DisplayPort protocol.

17. The method of claim 13 , wherein the first bond wire and third bond wire are substantially parallel and adjacent to each other.

18. The method of claim 13 , wherein the second bond wire and third bond wire are substantially parallel and adjacent to each other.

19. The method of claim 14 , wherein the first routing path includes a metal trace.

20. The method of claim 15 , wherein the first metal trace and the second metal trace are laid out on different layers of the PCB.

Assignees

• Realtek Semiconductor Corp

Inventors

• Kuan Chi-Kung
• Lin Chia-Liang (Leon)

Classifications

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H04L12/66 Primary

  Arrangements for connecting between networks having differing types of switching systems, e.g. gateways · CPC title