Address-dependent key generator by XOR tree

Patent metadata

Field	Value
Publication number	US-10313128-B2
Application number	US-201414473006-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Aug 29, 2014
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A method of providing security in a computer system includes producing a plurality of sub-keys from key material and a respective address of a memory location in a memory and possibly other information. The method may include mixing the sub-keys together using a binary tree of exclusive-or operations, and to produce an intermediate result. The method may include performing a scrambling operation on the intermediate result to produce a key with which a block of ciphertext may be produced. And the method may include performing a write operation to write the block of ciphertext at the memory location having the respective address. In this regard, the memory may include a window of memory locations each of which stores a respective block of ciphertext produced with a respective key that changes from memory location to memory location.

First claim

What is claimed is:

1. A system for providing security in a computer system, the system comprising one or more logic circuits configured to at least:
receive a respective address of a memory location in a memory;
produce a plurality of sub-keys from random key material and based on random key material and based on the respective address, the plurality of sub-keys being a plurality of blocks of random numbers;
mix the plurality of sub-keys together to produce an intermediate result, the plurality of sub-keys being mixed using a binary tree of multiple levels of bitwise exclusive-or operations;
perform a scrambling operation on the intermediate result to produce a key;
produce a block of ciphertext with the key; and
perform a write operation to write the block of ciphertext at the memory location having the respective address,
wherein the memory includes a window of memory locations each of which stores a respective block of ciphertext produced with a respective key that changes from memory location to memory location, the key is produced further based on a version value that is updated with each write operation at the memory location having the respective address, and each memory location of the window of memory locations stores the respective block of ciphertext produced with the respective key that also depends on the version value and thereby changes with each write operation,
wherein the respective address and version value are composed of respective sub-sequences of bits that concatenated form a sequence of bits at respective bit positions, and the random key material is composed of a sequence of blocks of random numbers at respective block positions, and
wherein the one or more logic circuits being configured to produce the plurality of sub-keys includes being configured to produce the plurality of sub-keys further from the version value, including the one or more logic circuits being configured to identify a plurality of bits from the sequence of bits, and select the plurality of blocks from the sequence of blocks at respective positions corresponding to those of the plurality of bits, the plurality of blocks being selected as the plurality of sub-keys.

2. The system of claim 1 , wherein the respective address is composed of a sequence of bits at respective positions, and the random key material is composed of a sequence of blocks of random numbers at respective positions, and
wherein the one or more logic circuits being configured to produce the plurality of sub-keys includes being configured to identify a plurality of bits from the sequence of bits, and select the plurality of blocks from the sequence of blocks at respective positions corresponding to those of the plurality of bits, the plurality of blocks being selected as the plurality of sub-keys.

3. The system of claim 2 , wherein the one or more logic circuits being configured to identify the plurality of bits includes being configured to identify only those bits of the sequence of bits having a preset binary value.

4. The system of claim 2 , wherein the sequence of blocks includes a first sequence of blocks of random numbers and a second sequence of blocks of random numbers,
wherein the one or more logic circuits being configured to identify the plurality of bits includes being configured to identify as a first one or more bits those bits of the sequence of bits having a binary value of one, and identify as a second one or more bits those bits of the sequence of bits having a binary value of zero, and
wherein the one or more logic circuits being configured to select the plurality of blocks includes being configured to select one or more blocks from the first sequence of blocks at respective positions corresponding to those of the first one or more bits, and select one or more blocks from the second sequence of blocks at respective positions corresponding to those of the second one or more bits.

5. The system of claim 1 , wherein the one or more logic circuits being configured to mix the plurality of sub-keys includes being configured to mix the plurality of sub-keys together and with at least a portion of the version value.

6. The system of claim 1 , wherein the one or more logic circuits being configured to perform the scrambling operation includes being configured to perform the scrambling operation on the version value added to the intermediate result.

7. The system of claim 1 , wherein the one or more logic circuits being configured to perform the scrambling operation includes being configured to cipher the intermediate result with another key to produce the key.

8. The system of claim 1 , wherein the one or more logic circuits being configured to perform the scrambling operation includes being configured to perform the scrambling operation with an increased-sized, reduced-round cipher, a permutation defined by one or more rotate-add-exclusive-or operations, or one or more layers of substitution boxes.

9. A method of providing security in a computer system, the method comprising:
receiving a respective address of a memory location in a memory;
producing a plurality of sub-keys from random key material and based on random key material and based on the respective address, the plurality of sub-keys being a plurality of blocks of random numbers;
mixing the plurality of sub-keys together to produce an intermediate result, the plurality of sub-keys being mixed using a binary tree of multiple levels of bitwise exclusive-or operations;
performing a scrambling operation on the intermediate result to produce a key;
producing a block of ciphertext with the key; and
performing a write operation to write the block of ciphertext at the memory location having the respective address,
wherein the memory includes a window of memory locations each of which stores a respective block of ciphertext produced with a respective key that changes from memory location to memory location, the key is produced further based on a version value that is updated with each write operation at the memory location having the respective address, and each memory location of the window of memory locations stores the respective block of ciphertext produced with the respective key that also depends on the version value and thereby changes with each write operation,
wherein the respective address and version value are composed of respective sub-sequences of bits that concatenated form a sequence of bits at respective bit positions, and the random key material is composed of a sequence of blocks of random numbers at respective block positions, and
wherein producing the plurality of sub-keys includes producing the plurality of sub-keys further from the version value, including identifying a plurality of bits from the sequence of bits, and selecting the plurality of blocks from the sequence of blocks at respective positions corresponding to those of the plurality of bits, the plurality of blocks being selected as the plurality of sub-keys.

10. The method of claim 9 , wherein the respective address is composed of a sequence of bits at respective positions, and the random key material is composed of a sequence of blocks of random numbers at respective positions, and
wherein producing the plurality of sub-keys includes identifying a plurality of bits from the sequence of bits, and selecting the plurality of blocks from the sequence of blocks at respective positions corresponding to those of the plurality of bits, the plurality of blocks being selected as the plurality of sub-keys.

11. The method of claim 10 , wherein identifying the plurality of bits includes identifying only those bits of the sequence of bits having a preset binary value.

12.

Assignees

• Boeing Co

Inventors

• Hars Laszlo
• Matthews Donald P

Classifications

• H04L9/002

  Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441) · CPC title

• G06F21/78

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

• G06F12/1408

  by using cryptography (for digital transmission H04L9/00) · CPC title

• H04L9/0861

  Generation of secret information including derivation or calculation of cryptographic keys or passwords · CPC title

• H04L9/3242 Primary

  involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC · CPC title