Error correction code in memory

Patent metadata

Field	Value
Publication number	US-10312943-B2
Application number	US-201715468619-A
Country	US
Kind code	B2
Filing date	Mar 24, 2017
Priority date	Mar 24, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

First claim

The invention claimed is:

1. A system comprising:
a plurality of memory dies on a memory module, wherein a plurality of data blocks are spread across the plurality of memory dies;
a first region of memory allocated for primary error correcting code (ECC) spread across at least a first subset of a first memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block;
a second region of memory allocated for secondary ECC spread across at least a second subset of the first memory die and a third subset of a second memory die included in the plurality of memory die; and
a memory controller configured to:
determine that an error within a first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block from the first region of memory;
access the second region allocated for secondary ECC stored at least on the first and second memory die, wherein the first region allocated for primary ECC is separate from the second region; and
correct the error using the primary and secondary ECC.

2. The system of claim 1 , the memory controller configured to:
perform a write to the first data block;
perform a primary ECC write to first portion of the primary ECC allocated to the first data block;
write contents of a secondary ECC write for the secondary ECC portion in an accumulation buffer;
determine that the accumulation buffer is to be flushed to memory; and
perform the secondary ECC write to the secondary ECC portion.

3. The system of claim 2 , the memory controller configured to:
determine that a second secondary FCC portion spread across a first die that does not share an electrical interface with the at least one die;
determine that the accumulation buffer includes a second secondary ECC write corresponding to a fifth data block having a second secondary ECC portion spread across the first die that does not share the electrical interface with the at least one die; and
performing the first and second secondary ECC writes in parallel.

4. The system of claim 1 comprising a plurality of electrical interfaces, each electrical interface connected to at least one memory die collectively holding the first secondary ECC portion.

5. The system of claim 1 wherein the secondary ECC is stored on a first ECC portion of a third data block on the third die and a second ECC portion of the third data block on the fourth die, wherein the first ECC portion and the fourth portion provide secondary ECC for a fourth data block.

6. The system of claim 5 , wherein an accumulation buffer has a plurality of flags corresponding to a plurality of accumulation buffer entries, each accumulation buffer entry corresponding to a combination of rank, bank, and interface, the memory controller configured to:
determine, based on the corresponding flag, that a corresponding write exists in the accumulation buffer for a first entry corresponding to a data block belonging to the plurality of data blocks; and
writing contents of a first accumulation buffer entry to memory.

7. The system of claim 1 Therein the first subset, storing the first region of memory allocated for primary ECC, includes a memory die on a first rank of memory die and the second subset, storing the second region of memory allocated for secondary ECC, includes a memory die on a second rank of memory die.

8. The system of claim 1 wherein the plurality of memory die includes ten memory die, a first plurality of regions, including the first region, allocated for primary ECC, a second plurality of regions, including the second regions, allocated for secondary ECC and each of the data blocks in the plurality of data blocks is within the ten memory die.

9. A method comprising:
determining, by a memory controller, that a first portion of primary ECC is not sufficient to correct an error within a first data block, wherein a first region of memory allocated for primary error correcting code (ECC) is spread across at least a first subset of a first memory die belonging to a plurality of memory die on a memory module;
accessing, by the memory controller, a second portion of a secondary ECC, wherein a second region of memory allocated for the secondary ECC is spread across at least a second subset of the first memory die and a third subset of a second memory die belonging to the plurality of memory die and the first region is separate from the second region; and
correcting, by the memory controller, the error using the primary and secondary ECC.

10. The method of claim 9 comprising:
performing a write to the first data block;
performing a primary ECC write to first portion of the primary ECC allocated to the first data block;
writing contents of a secondary ECC write for the secondary ECC portion in an accumulation buffer;
determining that the accumulation buffer is to be flushed to memory; and
writing the secondary ECC write to the secondary ECC portion.

11. The method of claim 10 , comprising:
determining that the accumulation buffer includes a second secondary ECC write corresponding to a fourth data block having a second secondary ECC portion spread across the at least one die belonging to the plurality of die; and
performing the first and second secondary ECC writes.

12. The method of claim 10 , comprising:
determining that a first die that does not share an electrical interface with the at least one die;
determining that the accumulation buffer includes a second secondary ECC write corresponding to a fifth data block having a second secondary ECC portion spread across the first die that does not share the electrical interface with the at least one die; and
performing the first and second secondary ECC writes in parallel.

13. The method of claim 10 , wherein an accumulation buffer has a flag corresponding to each memory address in the data block indicating whether a write for that memory address is in the accumulation buffer, the method comprising:
determining, based on the corresponding flag, that a corresponding write exists in the accumulation buffer for each memory address in the third data block and a fifth data block corresponding to the secondary ECC; and
writing the contents of a first accumulation buffer entry to memory.

14. The method of claim 10 , wherein a plurality of electrical interfaces connect the plurality of memory die, each electrical interface connected to at least one memory die collectively holding the first secondary ECC portion.

15. A system comprising:
a primary ECC handler to determine that a first portion of primary ECC is not sufficient to correct an error within a first data block, wherein a first region of memory allocated for primary error correcting code (ECC) spread across a first subset of at least one memory die belonging to a plurality of memory die on a memory module;
a secondary ECC handler to access a portion of a secondary ECC, wherein a second region of memory allocated for secondary ECC is spread across at least a second subset of the first memory die and a third subset of a second memory die belonging to the plurality of memory die and the first region is separate from the second region; and
an error corrector to correct the error using the primary and secondary ECC.

16. The system of claim 15 wherein the plurality of memory die includes ten memory die, a first plurality of regions, including the first region, allocated for primary ECC, a second plurality of regions, including the second regions, allocated for secondary ECC and each of the data blocks in the plurality of data blocks is wi

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Lesartre Gregg B
• Warner Craig
• Foltin Martin
• Brueggen Chris Michael
• Birk Brian S
• Ray Harvey

Classifications

• G11C2029/0411

  Online error correction · CPC title

• G11C2029/0409

  Online test · CPC title

• H03M13/2906 Primary

  using block codes (H03M13/2957 takes precedence) · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title