Successive approximation analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10312932-B2
Application number	US-201815924945-A
Country	US
Kind code	B2
Filing date	Mar 19, 2018
Priority date	Sep 1, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

The resolution of a successive approximation analog-to-digital converter is varied in a wide range. Provided is a successive approximation analog-to-digital converter including a digital-to-analog converter that generates an analog voltage based on a digital code, a comparator to which the analog voltage as the output of the digital-to-analog converter is inputted, a DAC control circuit that generates the digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on the output of the comparator, a delay circuit that starts the determination of the comparator by signal transition generated by delaying the signal state change of the output of the comparator, a clock generation circuit that generates a signal starting the determination of the comparator, and a selector circuit that selects a signal generated by the delay circuit or a signal generated by the clock generation circuit to feed the selected signal to the comparator.

First claim

The invention claimed is:

1. A successive approximation analog-to-digital converter that has:
a plurality of capacitive elements that sample an analog input signal and have weighted capacitance values;
a comparator that compares the analog input signal and a reference analog signal to output a comparison result;
a plurality of registers that store digital data based on the comparison result; and
a DAC that generates the reference analog signal based on the contents of the plurality of registers,
wherein the analog input signal is converted to a digital code by successively changing the digital data based on the output of the comparator,
the successive approximation analog-to-digital converter comprising:
a first timing signal generation unit that generates a first timing signal based on the output of an oscillation circuit;
a second timing signal generation unit that generates a second timing signal based on the state change of the output of the comparator; and
a selector circuit that selects the first timing signal or the second timing signal to feed the selected timing signal to the comparator.

2. The successive approximation analog-to-digital converter according to claim 1 , further comprising a control circuit that changes the number of the plurality of capacitive elements that sample the analog input signal, and changes the number of bits of the digital code.

3. The successive approximation analog-to-digital converter according to claim 2 ,
wherein the control circuit switches the selector circuit with the changing of the number of bits of the digital code.

4. The successive approximation analog-to-digital converter according to claim 2 ,
wherein the selector circuit selects the first timing signal when the number of bits of the digital code is equal to or more than a predetermined threshold value, and
wherein the selector circuit selects the second timing signal when the number of bits of the digital code is less than the threshold value.

5. The successive approximation analog-to-digital converter according to claim 2 ,
wherein the second timing signal generation unit has:
a logic circuit that generates a conversion completion signal based on the state change of the output of the comparator; and
a delay generation circuit that delays the conversion completion signal to generate the second timing signal.

6. The successive approximation analog-to-digital converter according to claim 5 ,
wherein the second timing signal generation unit delays the timing of the sampling completion of the analog input signal to generate a first second timing signal, and delays the conversion completion signal to generate a second or subsequent second timing signals.

7. The successive approximation analog-to-digital converter according to claim 5 ,
wherein the delay amount of the delay generation circuit is variable, and
wherein the control circuit changes the delay amount with the changing of the number of bits of the digital code.

8. The successive approximation analog-to-digital converter according to claim 5 ,
wherein a fetching timing of the data of the plurality of registers is controlled at a timing based on the first timing signal in a first mode in which the first timing signal is fed to the comparator, and
wherein the fetching timing of the data of the plurality of registers is controlled at a timing based on the conversion completion signal in a second mode in which the second timing signal is fed to the comparator.

9. The successive approximation analog-to-digital converter according to claim 8 , further comprising a selector for the registers for switching the timing signal fed to the plurality of registers,
wherein the selector for the registers performs switching in synchronization with the selector circuit.

10. The successive approximation analog-to-digital converter according to claim 5 ,
wherein a fetching timing of the data of the plurality of registers is controlled at a timing based on the conversion completion signal in the first mode in which the first timing signal is fed to the comparator, and
wherein the fetching timing of the data of the plurality of registers is also controlled at a timing based on the conversion completion signal in the second mode in which the second timing signal is fed to the comparator.

11. A successive approximation analog-to-digital converter comprising:
a digital-to-analog converter that generates an analog voltage based on a digital code;
a comparator to which the analog voltage as the generated analog voltage from the digital-to-analog converter is inputted;
a DAC control circuit that generates a digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on an output of the comparator;
a delay circuit that starts a determination of the comparator by signal transition generated by delaying a signal state change of the output of the comparator;
a clock generation circuit that generates a signal starting the determination of the comparator; and
a selector circuit that selects a signal generated by the delay circuit or a signal generated by the clock generation circuit to feed a selected signal to the comparator.

Assignees

• Hitachi Ltd

Inventors

• Nakamura Yohei
• Yamawaki Taizo

Classifications

• H03M1/125 Primary

  Asynchronous, i.e. free-running operation within each conversion cycle · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/007

  among different resolutions · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title