On-chip waveform measurement

Patent metadata

Field	Value
Publication number	US-10312892-B2
Application number	US-201715420191-A
Country	US
Kind code	B2
Filing date	Jan 31, 2017
Priority date	Jan 31, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.

First claim

What is claimed is:

1. A circuit for measuring a transition time of a digital signal, said circuit comprising:
a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage; and
a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal, wherein said time-difference-to-digital converter comprises a first programmable delay line and/or a second programmable delay line,
wherein said time-difference-to-digital converter comprises a phase detector, said first programmable delay line being arranged to forward said first signal to said phase detector with a first programmable delay applied and/or said second programmable delay line being arranged to forward said second signal to said phase detector with a second programmable delay applied, and
wherein said phase detector comprises a control circuit operable iteratively adjusting said first and/or said second delay until a phase difference detected by said phase detector is below a predefined threshold value and for determining said transition time from said first and/or second delay.

2. The circuit according to claim 1 , wherein said time-difference-to-digital converter is operable in a rise time measurement mode for converting a delay between a rising edge of said first signal and a rising edge of said second signal to said digital value so that said transition time characterizes a rise time of said digital signal.

3. The circuit according to claim 1 , wherein said time-difference-to-digital converter is operable in a fall time measurement mode to convert said delay between a falling edge of said first signal and a falling edge of said second signal to said digital value so that said transition time characterizes a fall time of said digital signal.

4. The circuit according to claim 1 , wherein said time-difference-to-digital converter also comprises an edge detection circuitry comprising a first multiplexer and a second multiplexer switchable by said control circuit,
wherein an output line of said first multiplexer is either an output signal of said programmable delay line or an inverted output signal of said first programmable delay line, and
wherein an output line of said second multiplexer is either said output signal of said second programmable delay line or an inverted output signal of said second programmable delay line.

5. The circuit according to claim 4 , wherein said output of said first multiplexer is connected to a first input line of said phase detector, and wherein said output of said second multiplexer is connected to a second input line of said phase detector.

6. The circuit according to claim 4 , wherein said phase detector comprises a first D-flip-flop whose input line is connected to said output line of said first multiplexer and whose clock input line is connected to said output line of said second multiplexer.

7. The circuit according to claim 6 , wherein said phase detector comprises also a synchronizer circuitry comprising a predefined number of cascaded D-flip-flops being clocked by a clock signal from said control circuit and operable for outputting a sense signal being used as input line of said control circuit.

8. The circuit according to claim 1 , wherein said first programmable delay line and/or a second programmable delay line are each organized in a hot-1 coding manner.

Assignees

• IBM

Inventors

• Arp Andreas
• Cilek Fatih
• Koch Michael V
• Ringe Matthias

Classifications

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• G01R25/005

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal · CPC title

• H03K5/04 Primary

  by increasing duration; by decreasing duration · CPC title

• H03K5/26

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title