Self-biasing integrated oscillator without bandgap reference

Patent metadata

Field	Value
Publication number	US-10312887-B2
Application number	US-201615365605-A
Country	US
Kind code	B2
Filing date	Nov 30, 2016
Priority date	Nov 30, 2016
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

An integrated oscillator has an R-S flipflop; a first and second capacitor; a current source transistor; first and second current-steering transistors, each having a source coupled to the current source transistor, with drains coupled to the first and second capacitor respectively. The first current-steering transistor has gate coupled to a first output of the R-S flipflop, and the second current-steering transistor has gate coupled to a second output of the R-S flipflop. The oscillator has a first sense inverter having input from the first capacitor and powered by a feedback circuit adapted to sense voltages on the first and second capacitor; and a second sense inverter having input from the second capacitor and powered by the feedback circuit. The R-S flipflop has a first input coupled to an output of the first sense inverter and a second input coupled to an output of the second sense inverter.

First claim

What is claimed is:

1. An integrated oscillator comprising:
an R-S flipflop;
a first and a second capacitor;
a first current source transistor having a drain and a gate;
a first and a second current-steering transistor, each having a source coupled to the drain of the first current source transistor, a drain of the first current-steering transistor coupled to the first capacitor, and a drain of the second current-steering transistor coupled to the second capacitor, the first current-steering transistor having a gate coupled to a first output of the R-S flipflop, and the second current-steering transistor having a gate coupled to a second output of the R-S flipflop;
a first sense inverter having input coupled to the first capacitor, the first sense inverter being powered by a feedback circuit adapted to sense voltages on the first and second capacitor; and
a second sense inverter having input coupled to the second capacitor and powered by the feedback circuit;
wherein the R-S flipflop has a first input coupled to an output of the first sense inverter and a second input coupled to an output of the second sense inverter; and
wherein the first input of the R-S flipflop is an active-low SET input.

2. An integrated oscillator comprising:
an R-S flipflop;
a first and a second capacitor;
a first current source transistor having a drain and a gate;
a first and a second current-steering transistor, each having a source coupled to the drain of the first current source transistor, a drain of the first current-steering transistor coupled to the first capacitor, and a drain of the second current-steering transistor coupled to the second capacitor, the first current-steering transistor having a gate coupled to a first output of the R-S flipflop, and the second current-steering transistor having a gate coupled to a second output of the R-S flipflop;
a first sense inverter having input coupled to the first capacitor, the first sense inverter being powered by a feedback circuit adapted to sense voltages on the first and second capacitor; and
a second sense inverter having input coupled to the second capacitor and powered by the feedback circuit;
wherein the R-S flipflop has a first input coupled to an output of the first sense inverter and a second input coupled to an output of the second sense inverter; and
wherein the feedback circuit comprises a first differential amplifier having an inverting and a noninverting input, the inverting input coupled through a first resistor to the first capacitor and through a second resistor to the second capacitor, and a third capacitor coupled between the inverting input and an output of the differential amplifier.

3. The integrated oscillator of claim 2 wherein the gate of the first current source transistor is coupled to an output of a bias circuit comprising an reference inverter having input coupled to output, a second differential amplifier having a noninverting input coupled to the output of the reference inverter and an inverting input coupled to the output of the bias circuit.

4. The integrated oscillator of claim 3 wherein the reference inverter has a threshold matched to the first sense inverter.

5. The integrated oscillator of claim 2 wherein the R-S flipflop has at least one additional input configured to place the R-S flipflop in a known state for testing.

6. The integrated oscillator of claim 1 wherein the R-S flipflop has at least one additional input configured to place the R-S flipflop in a known state for testing.

7. A method of generating a signal comprising:
generating a first controlled current;
switching the first controlled current onto a selected capacitor, the selected capacitor selected from the group consisting of a first capacitor and a second capacitor according to at least one output of an R-S flipflop;
detecting a voltage on the first capacitor reaching an oscillator threshold voltage and switching a state of the R-S flipflop; and
detecting a voltage on the second capacitor reaching the oscillator threshold voltage and switching the state of the R-S flipflop;
wherein the oscillator threshold voltage is a threshold voltage of a reference inverter comprising an N type transistor having source coupled to ground, gate coupled to input of the inverter, and drain coupled to output of the inverter, a P type transistor having source coupled to a control voltage, gate coupled to an input of the inverter, and drain coupled to the output of the inverter.

8. The method of claim 7 wherein the reference inverter is matched to a sense inverter that detects the voltage on the first capacitor.

9. The method of claim 7 wherein the control voltage is determined by a feedback control circuit having input from the voltage on the first capacitor and the voltage on the second capacitor.

Assignees

• Omnivision Tech Inc

Inventors

• Yang Li
• Wu Charles Qingle

Classifications

• H03K3/354

  Astable circuits · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K3/011

  Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} · CPC title

• H03B5/24 Primary

  active element in amplifier being semiconductor device (H03B5/26 takes precedence) · CPC title

• H03K3/0231 Primary

  Astable circuits {(H03K3/0315 takes precedence)} · CPC title