Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip

Patent metadata

Field	Value
Publication number	US-10312401-B2
Application number	US-201515115242-A
Country	US
Kind code	B2
Filing date	Feb 13, 2015
Priority date	Feb 17, 2014
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A method for producing an electronic semiconductor chip and a semiconductor chip are disclosed. In embodiments, the method includes providing a growth substrate having a growth surface formed by a flat region having a plurality of three-dimensional surface structures on the flat region, directly applying a nucleation layer of oxygen-containing AlN over a large area to the growth surface and growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence includes selectively growing the semiconductor layer sequence upwards from the flat region.

First claim

The invention claimed is:

1. A method for producing an electronic semiconductor chip, the method comprising:
providing a growth substrate comprising a growth surface formed by a planar region having a plurality of three-dimensional surface structures on the planar region;
directly applying a nucleation layer of oxygen-containing AlN over a large area to the growth surface;
growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence comprises selectively growing the semiconductor layer sequence upwards from the planar region such that a growth of the semiconductor layer sequence on the whole surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region; and
directly applying a nucleation layer of oxygen-containing AlN in such a way that the entire growth surface, the entire planar region and the surface structures are covered by the nucleation layer, wherein an oxygen content of the nucleation layer is more than 10 19 cm −3 , and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by the oxygen content of the nucleation layer.

2. The method according to claim 1 , wherein the three-dimensional surface structures are substantially covered by the semiconductor layer sequence while growing the semiconductor layer sequence.

3. The method according to claim 1 , wherein applying the nucleation layer is ensued by a metal-organic vapor-phase epitaxy.

4. The method according to claim 1 , wherein applying the nucleation layer is ensued by sputtering.

5. The method according to claim 1 , wherein the three-dimensional surface structures comprise conical or pyramidal elevations on the planar region.

6. The method according to claim 1 , wherein the growth substrate comprises aluminum oxide.

7. The method according to claim 6 , wherein the planar region is a crystallographic c surface.

8. The method according to claim 1 , wherein the semiconductor layer sequence is grown with an optoelectronic active layer, which is provided for emitting or detecting light during operation of the semiconductor chip.

9. The method according to claim 8 , wherein the semiconductor chip is designed as a light-emitting or light-detecting diode.

10. An electronic semiconductor chip comprising:
a growth substrate with a growth surface, which is formed by a planar region having a plurality of three-dimensional surface structures on the planar region;
a nucleation layer composed of oxygen-containing AlN directly disposed on the growth surface;
a nitride-based semiconductor layer sequence disposed on the nucleation layer, wherein the semiconductor layer sequence is selectively grown from the planar region such that a growth of the semiconductor layer sequence on the whole surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region; and
a nucleation layer of oxygen-containing AlN is directly applied in such a way that the entire growth surface, the entire planar region and the surface structures are covered by the nucleation layer, wherein an oxygen content of the nucleation layer is more than 10 19 cm −3 , and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by the oxygen content of the nucleation layer.

11. The method according to claim 1 , wherein the nucleation layer is applied to the growth surface with a thickness of greater than or equal to 1 nm, and wherein the nucleation layer is applied by sputtering or MOVPE.

12. The method according to claim 1 , wherein the nucleation layer is applied to the growth surface with a thickness of greater than or equal to 5 nm.

13. The method according to claim 1 , wherein a weight proportion of oxygen in the nucleation layer is greater than or equal to 0.1%.

14. A method for producing an electronic semiconductor chip, the method comprising:
providing a growth substrate comprising a growth surface formed by a planar region having a plurality of three-dimensional surface structures on the planar region;
directly applying a nucleation layer of oxygen-containing AlN over a large area to the growth surface;
growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence comprises selectively growing the semiconductor layer sequence upwards from the planar region such that a growth of the semiconductor layer sequence on the whole surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region; and
directly applying a nucleation layer of oxygen-containing AlN in such a way that the entire growth surface, the entire planar region and the surface structures are covered by the nucleation layer, wherein an oxygen content of the nucleation layer is more than 10 19 cm −3 , and wherein the oxygen content of the nucleation layer is adjusted in such a way that the semiconductor layer sequence is predominantly grown from the planar region, whereas very little or no growth at all of the semiconductor layer sequence takes place on the three-dimensional surface structures.

Assignees

• Osram Opto Semiconductors Gmbh

Inventors

• Bergbauer Werner
• Lehnhardt Thomas
• Off Jürgen
• Hertkorn Joachim

Classifications

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2925 Primary

  Surface structures · CPC title

• H10P14/276

  Lateral overgrowth · CPC title