Semiconductor device with contamination improvement

Patent metadata

Field	Value
Publication number	US-10312366-B2
Application number	US-201715663636-A
Country	US
Kind code	B2
Filing date	Jul 28, 2017
Priority date	Aug 29, 2015
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate, wherein:
the substrate has at least two device regions separated by at least one isolation structure which is disposed in the substrate, and
each of the device regions comprises two doped regions disposed in the substrate;

two gate structures respectively disposed on the device regions, wherein in each of the device regions, the doped regions are respectively disposed at two opposite sides of the gate structure;
an etching stop layer disposed over the substrate and peripherally surrounding the gate structures;
an interlayer dielectric layer disposed over the etching stop layer; and
a material layer disposed on the interlayer dielectric layer, wherein:
a material forming the material layer is metal,
at a smallest distance between the material layer and a first gate structure of the gate structures, the material layer is separated from the first gate structure by the etching stop layer and a spacer disposed between the first gate structure and the etching stop layer,
the material layer has a top surface which is elevated at the same level with top surfaces of the gate structures,
a ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures substantially ranges from 1/30 to 1/80, and
a ratio of the thickness of the thickest portion of the material layer to a thickness of a thickest portion of the interlayer dielectric layer is greater than 0 and smaller than 1/30.

2. The semiconductor device of claim 1 , wherein each of the gate structures comprises:
a gate dielectric layer disposed on the substrate; and
a gate electrode disposed on the gate dielectric layer.

3. The semiconductor device of claim 2 , wherein each of the gate electrodes is formed from metal.

4. The semiconductor device of claim 1 , wherein:
the doped regions of a first device region of the device regions are equal in size to the doped regions of a second device region one of the device regions, and
a top surface of an isolation structure between a first doped region of the doped regions of the first device region and a second doped region of the doped regions of the second device region is not higher than the first doped region and is not higher than the second doped region.

5. The semiconductor device of claim 1 , wherein the thickest portion of the material layer overlies the isolation structure.

6. The semiconductor device of claim 1 , wherein the material layer has a convex surface.

7. The semiconductor device of claim 6 , wherein:
the interlayer dielectric layer has a concave surface, and
the convex surface is in contact with the concave surface.

8. A semiconductor device, comprising:
a substrate;
two gate structures disposed on the substrate and separated from each other, wherein:
two doped regions are respectively disposed at two opposite sides of each of the gate structures,
the doped regions disposed at two opposite sides of a first gate structure of the gate structures are equal in size to the doped regions disposed at two opposite sides of a second gate structure of the gate structures, and
a top surface of an isolation structure between a first doped region of the doped regions disposed at two opposite sides of the first gate structure and a second doped region of the doped regions disposed at two opposite sides of the second gate structure is not higher than the first doped region and is not higher than the second doped region;

an etching stop layer covering the substrate and the doped regions, and peripherally surrounding the gate structures;
an interlayer dielectric layer disposed on the etching stop layer, wherein a top of the interlayer dielectric layer has at least one concave surface; and
a material layer disposed on the at least one concave surface of the interlayer dielectric layer, wherein:
a material forming the material layer is metal,
at a smallest distance between the material layer and the first gate structure, the material layer is separated from the first gate structure by the etching stop layer and a spacer disposed between the first gate structure and the etching stop layer,
the material layer has a top surface which is elevated at the same level with top surfaces of the gate structures, and
a ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures substantially ranges from 1/30 to 1/80.

9. The semiconductor device of claim 8 , wherein each of the gate structures comprises:
a gate dielectric layer disposed on the substrate; and
a gate electrode disposed on the gate dielectric layer.

10. The semiconductor device of claim 8 , wherein a material forming the etching stop layer is different from a material forming the interlayer dielectric layer.

11. The semiconductor device of claim 8 , wherein the interlayer dielectric layer is formed from flowable oxide.

12. The semiconductor device of claim 8 , wherein a ratio of the thickness of the thickest portion of the material layer to a thickness of a thickest portion of the interlayer dielectric layer is substantially greater than 0 and smaller than 1/30.

13. The semiconductor device of claim 8 , wherein the thickest portion of the material layer overlies the isolation structure.

14. A semiconductor device, comprising:
a substrate;
two gate structures disposed on the substrate, wherein:
the gate structures are separated by an isolation structure which is disposed in the substrate,
two doped regions are respectively disposed at two opposite sides of each of the gate structures, and
the doped regions disposed at two opposite sides of one of the gate structures are equal in size to the doped regions disposed at two opposite sides of another one of the gate structures;

two spacers peripherally surrounding the gate structures respectively, wherein the spacers have a tapered sidewall;
an etching stop layer covering the substrate, the isolation structure, the doped regions, and the spacers;
an interlayer dielectric layer disposed on the etching stop layer and peripherally surrounding the gate structures; and
a material layer disposed on the interlayer dielectric layer, wherein:
a material forming the material layer is metal,
at a smallest distance between the material layer and a first gate structure of the gate structures, the material layer is separated from the first gate structure by the etching stop layer and a first spacer of the spacers peripherally surrounding the first gate structure,
the material layer has a top surface which is elevated at the same level with top surfaces of the gate structures, and
a ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures substantially ranges from 1/30 to 1/80.

15. The semiconductor device of claim 14 , wherein a material forming the etching stop layer is different from a material forming the interlayer dielectric layer.

16. The semiconductor device of claim 14 , wherein the interlayer dielectric layer is formed from flowable oxide.

17. The semiconductor device of claim 14 , wherein a ratio of the thickness of the thickest portion of the material layer to a thickness of a thickest portion of the interlayer dielectric layer is substantially greater than 0 and smaller than 1/30.

18. The semiconductor device of claim 14 , wherein the thickest portion of the material layer is disposed at a midpoint between the gate structures.

19. The semiconductor device of claim 14 , wherein:
a first doped region of t

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Sun Chung-Ren
• Jangjian Shiu-Ko
• Chen Kun-Ei
• Lin Chun-Che

Classifications

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H01L29/6656

  Electricity · mapped topic

• H01L21/823437

  Electricity · mapped topic