Display device having LTPS and oxide TFTs integrated on the same substrate

US10312312B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10312312-B2
Application numberUS-201515520153-A
CountryUS
Kind codeB2
Filing dateDec 31, 2015
Priority dateDec 31, 2014
Publication dateJun 4, 2019
Grant dateJun 4, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a display device. A poly-Si layer is disposed on a substrate. A first metal layer is disposed on the poly-Si layer, and a metal oxide layer is disposed on the first metal layer. A second metal layer is disposed on the metal oxide layer. The first metal layer is overlapped with the second metal layer. The first metal layer and the second metal layer may be gate lines connected to different TFTs.

First claim

Opening claim text (preview).

The invention claimed is: 1. A display device comprising: a substrate; a polycrystalline silicon (poly-Si) layer on the substrate; a first metal layer on the poly-Si layer; a metal oxide layer on the first metal layer; a second metal layer disposed on the metal oxide layer and overlapped with the first metal layer; a capacitor in which a first sub-capacitor, a second sub-capacitor, and third sub-capacitor are connected in parallel to each other, two terminals of the first sub-capacitor are the poly-Si layer and the first metal layer, two terminals of the second sub-capacitor are the first metal layer and the metal oxide layer, and two terminals of the third sub-capacitor are the metal oxide layer and the second metal layer; and a first thin-film-transistor (TFT) and a second TFT are disposed in a pixel defined on the substrate, wherein the poly-Si layer is an active layer of the first TFT, and the metal oxide layer is an active layer of the second TFT connected to the second metal layer, and wherein the capacitor is provided in the pixel defined on the substrate. 2. The display device according to claim 1 , further comprising: a plurality of switching thin-film-transistors (TFTs) and a driving TFT disposed in the pixel defined on the substrate, wherein the first metal layer and the second metal layer are respectively connected to gate electrodes of different switching TFTs among the plurality of switching TFTs. 3. The display device according to claim 2 , wherein the first metal layer and the second metal layer are extended in the same direction. 4. The display device according to claim 2 , wherein the first metal layer and the second metal layer are gate lines. 5. The display device according to claim 2 , wherein one terminal of a switching TFT connected to the second metal layer is connected to a gate electrode of the driving TFT. 6. The display device according to claim 1 , further comprising: a driving circuit disposed in a non-display area of the substrate and implemented with a plurality of TFTs, wherein the first metal layer and the second metal layer are respectively connected to gate electrodes of different TFTs among the plurality of TFTs. 7. The display device according to claim 6 , wherein the driving circuit is a gate driver for providing one or more gate signals to the pixel defined on the substrate. 8. The display device according to claim 1 , wherein the poly-Si layer includes conductivized polycrystalline silicon, the metal oxide layer includes conductivized metal oxide, and the poly-Si layer, the first metal layer, the metal oxide layer and the second metal layer are overlapped with each other. 9. The display device according to claim 1 , further comprising: the first TFT is a first switching TFT having one terminal connected to a first node; a driving TFT having a gate electrode connected to the first node and one terminal connected to a second node; the second TFT is a second switching TFT having one terminal connected to the second node; and an organic light emitting diode connected to the second node, wherein the capacitor is connected between the first node and the second node. 10. The display device according to claim 9 , wherein the first metal layer includes the same material as a gate electrode of the second switching TFT, and the second metal layer includes the same material as a gate electrode of the first switching TFT. 11. The display device according to claim 9 , wherein the second switching TFT is an oxide TFT, and the first switching TFT and the driving TFT are low-temperature polycrystalline silicon (LTPS) TFTs. 12. The display device according to claim 9 , wherein the first metal layer and the second metal layer are connected to the first node, and the poly-Si layer and the metal oxide layer are connected to the second node. 13. The display device according to claim 1 , further comprising: a driving circuit disposed on a non-display area of the substrate and including the capacitor. 14. The display device according to claim 13 , wherein the driving circuit is a gate driver for providing one or more gate signals to the pixel defined on the substrate.

Assignees

Inventors

Classifications

  • in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

  • Change or adaptation of the frame rate of the video stream · CPC title

  • Wiring, e.g. gate line, drain line · CPC title

  • The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

  • Special arrangements specific to the use of low carrier mobility technology · CPC title

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What does patent US10312312B2 cover?
Provided is a display device. A poly-Si layer is disposed on a substrate. A first metal layer is disposed on the poly-Si layer, and a metal oxide layer is disposed on the first metal layer. A second metal layer is disposed on the metal oxide layer. The first metal layer is overlapped with the second metal layer. The first metal layer and the second metal layer may be gate lines connected to dif…
Who is the assignee on this patent?
Lg Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/13454. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 04 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).