Semiconductor devices

Patent metadata

Field	Value
Publication number	US-10312138-B2
Application number	US-201715467045-A
Country	US
Kind code	B2
Filing date	Mar 23, 2017
Priority date	Aug 16, 2016
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode structure including gate electrodes stacked on the substrate. The vertical channel structures extend in a first direction perpendicular to a top surface of the substrate. The gate electrodes include line regions and contact regions. The line regions extend from the main zone toward the extension zone along a second direction the second direction that is perpendicular to the first direction. The contact regions are on ends of the line regions and are thicker than the line regions. A spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a main zone and an extension zone;
vertical channel structures on the main zone, the vertical channel structures extending in a first direction perpendicular to a top surface of the substrate; and
an electrode structure including gate electrodes stacked on the substrate,
the gate electrodes including line regions and contact regions,
the line regions extending from the main zone toward the extension zone along a second direction that is perpendicular to the first direction,
the contact regions being on ends of the line regions,
the contact regions being thicker than the line regions,
an interface between the line regions and the contact regions being defined by a thickness transition, from a first thickness to a second thickness at terminal regions of the gate electrodes, measured from a lower surface of the gate electrodes to an upper surface of the gate electrodes,

the second thickness being greater than the first thickness, the contact regions having the second thickness, and
a spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions, wherein
each of the contact regions includes a top surface and a bottom surface,
a first width of the top surface is greater than a second width of the bottom surface, wherein
each of the contact regions comprises a lower portion connected to a corresponding one of the line regions and an upper portion protruding from a top surface of the corresponding one of the line regions such that the upper portion laterally protrudes over the corresponding one of the line regions.

2. The semiconductor device of claim 1 , wherein
the gate electrodes include a first gate electrode and a second gate electrode that are adjacent to each other in the first direction,
the second gate electrode is below the first gate electrode,
the first gate electrode includes a first line region and a first contact region, and
the second gate electrode includes a second line region and a second contact region.

3. The semiconductor device of claim 2 , wherein a distance between the first contact region and the second contact region is greater than a distance between a bottom surface of the first line region and a top surface of the second line region.

4. The semiconductor device of claim 2 , wherein a top surface of the second contact region is higher than a bottom surface of the first contact region.

5. The semiconductor device of claim 2 , wherein
the first contact region includes a first sidewall connected to a second sidewall, and
the first contact region includes a first portion extending along the first sidewall and a second portion extending along the second sidewall.

6. The semiconductor device of claim 1 , wherein
the contact regions include sidewalls,
the line regions include top surfaces, and
the sidewalls of the contact regions in direct contact with the top surfaces of the line regions make an acute angle with the top surfaces of the line regions.

7. The semiconductor device of claim 1 , wherein
a thickness of the contact regions decreases with as a distance from the line regions increases.

8. The semiconductor device of claim 1 , wherein
a width of a top surface of the upper portion is greater than a width of a bottom surface of the upper portion, and
an entirety of the upper portion of the contact region is at a height above the lower portion of the contact region and the top surface of the corresponding one of the line regions.

9. The semiconductor device of claim 1 , wherein
the line regions include a recession on portions thereof adjacent to the contact regions, and
the recession has a recessed top surface.

10. The semiconductor device of claim 1 , wherein the electrode structure includes:
a first stepwise structure where the contact regions are arranged along the second direction; and
a second stepwise structure where the contact regions are arranged along a third direction perpendicular to the first direction and the second direction.

11. The semiconductor device of claim 1 , further comprising;
insulation patterns between the gate electrodes; and
spacers on sidewalls of the contact regions, wherein
a material of the spacers is the same as a material of the insulation patterns.

12. The semiconductor device of claim 1 , wherein
the upper portion overlaps the corresponding one of the line regions, and
an entirety of the of the upper portion of the contact region is at a height above the lower portion of the contact region and the top surface of the corresponding one of the line regions.

13. A semiconductor device, comprising:
a substrate including a main zone and an extension zone;
an electrode structure including gate electrodes stacked on the substrate,
each of the gate electrodes including a line region and a contact region,
the line region extending from the main zone toward the extension zone,
the contact region on an end of the line region and thicker than the line region,
a top surface of the contact region being higher than a bottom surface of the line region of the gate electrode directly above the contact region,
an interface between the line region and the contact region in a corresponding gate electrode among the gate electrodes being defined by a thickness transition, from a first thickness to a second thickness at a terminal region of the corresponding gate electrode, measured from a lower surface of the corresponding gate electrode to an upper surface of the corresponding gate electrode,

the second thickness being greater than the first thickness, the contact region having the second thickness; and
vertical channel structures on the main zone, the vertical channel structures penetrating the electrode structure,
wherein each of the contact regions includes a lower portion connected to a corresponding one of the line regions and an upper portion protruding from a top surface of the corresponding one of the line regions such that the upper portion laterally protrudes over the corresponding one of the line regions, and
a width of a top surface of the upper portion is greater than a width of a bottom surface of the upper portion.

14. The semiconductor device of claim 13 , wherein
the upper portion of the gate electrodes has a sidewall protruding from a sidewall of the portion of the gate electrodes.

15. A semiconductor device, comprising:
a substrate; and
a memory cell array on the substrate,
the memory cell array including gate electrodes stacked on top of each other,

each of gate electrodes including a line region and a contact region connected to an end of the line region,
an interface between the line regions and the contact regions being defined by a thickness transition, from a first thickness to a second thickness at terminal regions of the gate electrodes, measured from a lower surface of the gate electrodes to an upper surface of the gate electrodes,

the second thickness being greater than the first thickness, the contact regions having the second thickness,
the gate electrodes including a first gate electrode over a second gate electrode,
the line regions of the first and second gate electrodes being separated from each other by a first distance in a first direction vertical to a top surface of the substrate,
the contact regions of the first and second gate electrodes being separated from each other by a second distance in a second direction that is parallel to the top surface of the substrate and less than the firs

Assignees

• Hyun Chung Il
• JANG Semee
• Lee Sung Yun
• Samsung Electronics Co Ltd

Inventors

• Hyun Chung-Il
• JANG Semee
• Lee Sung Yun

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L21/76877

  Electricity · mapped topic