Semiconductor devices with back surface isolation

Patent metadata

Field	Value
Publication number	US-10312131-B2
Application number	US-201715434611-A
Country	US
Kind code	B2
Filing date	Feb 16, 2017
Priority date	Dec 15, 2010
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

First claim

What is claimed is:

1. A method of forming an integrated device comprising a plurality of transistor devices, said method comprising:
providing a substrate, the substrate having a potential; and
forming the plurality of transistor devices on the substrate, comprising, for each of the transistor devices, the steps of:
forming a conductive well in the substrate, wherein the conductive well is electrically isolated in at least one bias polarity from the potential of the substrate;
forming at least one buffer layer over the substrate and the conductive well;
forming a device layer including a current conducting region over the at least one buffer layer;
forming a source contact and a drain contact on a top surface of the device layer and over the conductive well of the substrate;
forming a conductive via extending from the top surface of the device layer, through the device layer and the buffer layer to penetrate and terminate within the conductive well, and electrically connecting the conductive well to the source contact, such that a potential under the source contact and the drain contact is independent from the potential of the substrate, and the drain contact is independent in potential from a backside of the substrate; and
forming an isolation structure in the integrated device to isolate the conductive well of each of the transistor devices from the conductive well of neighboring transistor devices formed on the substrate, such that the potential under the source contact and the drain contact of each of the transistor devices is independent from the potential under the source contact and the drain contact of the neighboring transistor devices.

2. The method of claim 1 , wherein the isolation structure in the integrated device is formed by:
forming a photo-resist pattern definition over the device layer in a region between where the source contact and the drain contact are formed;
etching down through layers of the transistor devices in exposed areas of the photo-resist pattern at least below the conductive well;
and
filling the etched areas with an isolating material.

3. The method of claim 1 , wherein the isolation structure in the integrated device is formed by implanting isolating material into the transistor devices.

4. The method of claim 1 , wherein the isolation structure comprises an epitaxially-based substrate isolation structure by forming one or more substrate isolation layers between the substrate and the conductive well.

Assignees

• Efficient Power Conversion Corp
• Efficient Power Converson Corp

Inventors

• Lidow Alexander
• Cao Jianjun
• Beach Robert
• Strydom Johan T
• Nakata Alana
• Zhao Guangyuan

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title