Monolithic ceramic capacitor, monolithic ceramic capacitor array, and monolithic ceramic capacitor mounting structure

US10312025B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10312025-B2
Application numberUS-201816104299-A
CountryUS
Kind codeB2
Filing dateAug 17, 2018
Priority dateFeb 10, 2014
Publication dateJun 4, 2019
Grant dateJun 4, 2019

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A monolithic ceramic capacitor includes a plurality of first and second inner electrodes in a ceramic body. A direction in which the first and second inner electrodes are stacked is a stacking direction, a direction perpendicular or substantially perpendicular to the stacking direction in the ceramic body is a length direction, and a direction perpendicular or substantially perpendicular to the stacking direction and the first direction is a width direction. The ceramic body includes an effective portion, a first outer layer portion, a second outer layer portion, a first side portion, and a second side portion. A ratio A/B is about 0.04 or less when a dimension of each of the first side portion and the second side portion in the width direction is A and a dimension of the effective portion in the stacking direction is B.

First claim

Opening claim text (preview).

What is claimed is: 1. A monolithic ceramic capacitor comprising: a ceramic body including dielectric layers; and a plurality of first and second inner electrodes stacked so as to oppose each other via one of the dielectric layers interposed therebetween; wherein a direction in which the plurality of first and second inner electrodes are stacked is a stacking direction, a direction that is perpendicular or substantially perpendicular to the stacking direction is a length direction, and a direction that is perpendicular or substantially perpendicular to the stacking direction and to the first direction is a width direction; the ceramic body includes an effective portion including the plurality of first and second inner electrodes, a first outer layer portion and a second outer layer portion sandwiching the effective portion in the stacking direction, and a first side portion, and a second side portion sandwiching the effective portion in the width direction; when a dimension of each of the first side portion and the second side portion in the width direction is A, the dimension A is about 17 μm or less; when a dimension of the effective portion in the stacking direction is B and a thickness of the ceramic body is To, B/To is about 0.6 or more; when a dimension of the first outer layer portion is C, the dimension C is about 28 μm or less; and a maximum dimension among external dimensions of the monolithic ceramic capacitor is less than about 1.88 mm. 2. The monolithic ceramic capacitor according to claim 1 , wherein C>A is satisfied. 3. The monolithic ceramic capacitor according to claim 1 , wherein the dielectric layers interposed between adjacent first and second inner electrodes have a thickness of about 1 μm or smaller. 4. The monolithic ceramic capacitor according to claim 1 , wherein the first and second side portions cover side surfaces of the effective portion at which the first inner electrodes and the second inner electrodes are exposed at the effective portion and cover side surfaces of the first and second outer layer portions. 5. A monolithic ceramic capacitor array comprising: a carrier tape including a plurality of cavities; and a plurality of the monolithic ceramic capacitors according to claim 1 that are accommodated in the respective cavities; wherein the first and second inner electrodes of each monolithic ceramic capacitor are parallel or substantially parallel to a bottom surface of the corresponding cavity. 6. A monolithic ceramic capacitor mounting structure comprising: a board; and the monolithic ceramic capacitor according to claim 1 that is mounted on a surface of the board; wherein the stacking direction is perpendicular or substantially perpendicular to the surface of the board, and the first outer layer portion is positioned closer to the board than the second outer layer portion. 7. The monolithic ceramic capacitor mounting structure according to claim 6 , wherein an outer surface of the first outer layer portion that is perpendicular or substantially perpendicular to the stacking direction is a mounting surface; and C>A is satisfied. 8. The monolithic ceramic capacitor mounting structure according to claim 6 , wherein the dielectric layers interposed between adjacent first and second inner electrodes have a thickness of about 1 μm or smaller. 9. The monolithic ceramic capacitor mounting structure according to claim 6 , wherein the first and second side portions cover side surfaces of the effective portion at which the first inner electrodes and the second inner electrodes are exposed at the effective portion and cover side surfaces of the first and second outer layer portions.

Assignees

Inventors

Classifications

  • the terminals embracing or surrounding the capacitive element, e.g. caps (H01G4/252 takes precedence) · CPC title

  • H01G4/30Primary

    Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • Form of non-self-supporting electrodes · CPC title

  • Non-printed capacitor · CPC title

  • containing a glassy phase, e.g. glass ceramic · CPC title

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What does patent US10312025B2 cover?
A monolithic ceramic capacitor includes a plurality of first and second inner electrodes in a ceramic body. A direction in which the first and second inner electrodes are stacked is a stacking direction, a direction perpendicular or substantially perpendicular to the stacking direction in the ceramic body is a length direction, and a direction perpendicular or substantially perpendicular to the…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 04 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).