Memory and electronic devices with reduced operational energy in chalcogenide material

Patent metadata

Field	Value
Publication number	US-10311949-B2
Application number	US-201815864995-A
Country	US
Kind code	B2
Filing date	Jan 8, 2018
Priority date	Jun 8, 2009
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.

First claim

What is claimed is:

1. A memory device, comprising:
a chalcogenide material between a first electrode and a second electrode; and
a stress material surrounding a sidewall of the chalcogenide material, the stress material configured to apply a lateral stress upon the chalcogenide material in response to a temperature change or an electrical field,
the first electrode defining a lesser lateral width than a lateral width defined by the chalcogenide material.

2. The memory device of claim 1 , wherein the stress material has a coefficient of thermal expansion differing from a coefficient of thermal expansion exhibited by the chalcogenide material.

3. The memory device of claim 2 , wherein the stress material is directly laterally adjacent the chalcogenide material.

4. The memory device of claim 2 , wherein an upper surface of the stress material is coplanar with an upper surface of the chalcogenide material.

5. The memory device of claim 4 , wherein the stress material extends laterally adjacent at least a portion of the first electrode.

6. The memory device of claim 4 , wherein a lower surface of the stress material is coplanar with a lower surface of the chalcogenide material.

7. The memory device of claim 1 , wherein the stress material is a piezoelectric material.

8. The memory device of claim 7 , further comprising additional electrodes configured to apply the electrical field, the piezoelectric material being disposed between the additional electrodes.

9. The memory device of claim 7 , further comprising a dielectric material between the chalcogenide material and the piezoelectric material.

10. The memory device of claim 1 , wherein the chalcogenide material is selected from the group consisting of GeSbTe (GST), GeTe, AgInSbTe, InSe, SbSe, SbTe, InSbSe, InSbTe, GeSbSe, and GeSbTeSe.

11. A memory device, comprising:
a memory cell comprising:
a first electrode;
a second electrode; and
a chalcogenide material disposed between the first electrode and the second electrode, the chalcogenide material having a first coefficient of thermal expansion; and
a thermal expansion material at least partially surrounding the chalcogenide material of the memory cell, the thermal expansion material having a second coefficient of thermal expansion differing from the first coefficient of thermal expansion of the chalcogenide material, the thermal expansion material selected to stress the chalcogenide material upon heating or cooling of the thermal expansion material during operation of the memory device.

12. The memory device of claim 11 , wherein the chalcogenide material is wider than the first electrode.

13. The memory device of claim 11 , wherein the thermal expansion material extends entirely circumferentially around the chalcogenide material.

14. The memory device of claim 11 , wherein the second coefficient of thermal expansion is at least 1.5 times the first coefficient of thermal expansion.

15. The memory device of claim 11 , wherein the thermal expansion material comprises benzocyclobutene.

16. The memory device of claim 11 , wherein at least a portion of the thermal expansion material extends under a lower surface of the chalcogenide material.

17. An electronic device, comprising:
an array of memory devices, at least one memory device of the array comprising:
an upper electrode;
a lower electrode;
a chalcogenide material between the upper electrode and the lower electrode, the chalcogenide material extending laterally beyond a sidewall of the lower electrode; and
a stress material laterally adjacent the chalcogenide material and configured to apply a lateral stress upon the chalcogenide material in response to a temperature change or an electrical field.

18. The electronic device of claim 17 , wherein the stress material is not in physical contact with the lower electrode.

19. The electronic device of claim 17 , wherein the stress material is in physical contact with the lower electrode.

20. The electronic device of claim 17 , wherein the lower electrode comprises a conductive member in electrical contact with a resistive heating element structured to generate heat as current flows through the resistive heating element during operation of the memory device.

Assignees

• Micron Technology Inc

Inventors

• Meade Roy E

Classifications

• H01L45/144

  Electricity · mapped topic

• G11C2013/0095

  Write using strain induced by, e.g. piezoelectric, thermal effects · CPC title

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• H01L45/06

  Electricity · mapped topic

• G11C13/004

  Reading or sensing circuits or methods · CPC title