Memory management

Patent metadata

Field	Value
Publication number	US-10311241-B2
Application number	US-201715701517-A
Country	US
Kind code	B2
Filing date	Sep 12, 2017
Priority date	Dec 6, 2016
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code. The memory controller reads at least one octet including at least a portion of the read data item and at least a portion of the read data protection code from a read address.

First claim

The invention claimed is:

1. A system on a chip, comprising:
a data processor having a processor data word size of p×octets, wherein p is a positive integer, and configured to handle data items having a data item size which is a non-integer multiple of the processor data word size;
a memory controller for a memory, wherein the memory controller is configured to write data to, or read data from, the memory as multiples of m×, wherein m is a positive integer;
a bus over which data can be sent between the data processor and the memory controller;
a data protection code generator generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller, and wherein the memory controller is further configured to write at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address of the memory; and
a data protection code checker receive a read data protection code and a read data item received over the bus and to check the read data item for an error using the read data protection code, and wherein the memory controller is further configured to read at least one octet including at least a portion of the read data item at least a portion of the read data protection code from a read address of the memory; wherein the data protection code generator is arranged between the data processor and the bus to receive data items generated by the data processor and pass data items and associated data protection codes to the bus for transmission to the memory controller and the data processor is implemented using circuitry.

2. The system on a chip as claimed in claim 1 , wherein the data protection code checker is arranged between the data processor and the bus to receive data items and associated data protection codes sent over the bus by the memory controller and to pass data items to the data processor.

3. The system on a chip as claimed in claim 1 , wherein the data protection code generator and/or the data protection code checker is provided as part of the data processor.

4. The system on a chip as claimed in claim 1 , and further comprising a further data processor having a further processor data word size of p′×octets, wherein p′ is a positive integer, and configured to process data items having a data item size which is a non-integer multiple of the further processor data word size, wherein the data protection code checker is arranged between the further data processor and the bus to receive data items and associated data protection codes sent over the bus by the memory controller and to pass data items to the further data processor.

5. The system on a chip as claimed in claim 4 , wherein the data protection code generator is provided as part of the data processor and/or the data protection code checker is provided as part of the further data processor.

6. The system on a chip as claimed in claim 1 , wherein m≥2.

7. The system on a chip as claimed in claim 1 , wherein p and/or p′≥2, m is in the range from 2 to 8, and the bus has a width of b×octets, wherein b is a positive integer, and b is in the range from 1 to 32.

8. The system on a chip as claimed in claim 1 , wherein the data protection code generator is configured to cause the memory controller to store a further portion of the data item at a further address of the memory, and/or the data protection code checker is configured to cause the memory controller to retrieve a further portion of the read data item from a further read address of the memory.

9. The system on a chip as claimed in claim 8 , wherein the data protection code generator is further configured to cause the memory controller to store a further portion of the data protection code at the further address of the memory, and/or the data protection code checker is further configured to cause the memory controller to retrieve a further portion of the read data protection code from the further read address of the memory.

10. The system on a chip as claimed in claim 1 , wherein the at least a portion of the data item comprises the whole of the data item and/or the at least a portion of the read data item comprises the whole of the read data item, and wherein the data protection code generator is further configured to cause the memory controller to store the whole of the data item and the data protection code at the address of the memory, and/or the data protection code checker is further configured to cause the memory controller to retrieve the whole of the read data item and the read data protection code from the read address of the memory.

11. The system on a chip as claimed in claim 1 , wherein the data protection code is an error correction code or an error detection code.

12. The system on a chip as claimed in claim 1 and further comprising a memory in communication with the memory controller.

13. A data processing system comprising:
the system on a chip as claimed in claim 1 ; and
a memory in communication with the memory controller.

14. The system on a chip as claimed in claim 1 or the data processing system as claimed in claim 1 , wherein the memory controller is a DRAM controller and the memory is a DRAM.

15. A method of operating a system on a chip comprising a data processor having a processor data word size of p×, wherein p is a positive integer, and process data items having a data item size which is a non-integer multiple of the processor data word size,
a memory controller for a memory with a plurality of memory addresses and wherein the memory controller is configured to write data to, or read data from, the memory as multiples of m×octets, wherein m is a positive integer, and a bus over which data items can be transmitted between the data processor and the memory controller, the method comprising:
generating a data protection code, by a data protection code generator, for a data item generated by the data processor;
transmitting the data protection code and the data item over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code at an address in the memory;
receiving over the bus a read data protection code and a read data item retrieved by the memory controller reading at least one octet including at least a portion of the read data protection code and at least a portion of the read data item from a read address in the memory; checking the read data item for an error using the read data protection code; wherein the data protection code generator is arranged between the data processor and the bus to receive data items generated by the data processor and pass data items and associated data protection codes to the bus for transmission to the memory controller and the data processor is implemented using circuitry.

Assignees

• Nxp Usa Inc

Inventors

• Fader Joachim
• Krutsch Robert
• Wendel Dirk

Classifications

• G06F11/0727

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1052

  Bypassing or disabling error detection or correction · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title