Circuit verification on a distributed database processing system

Patent metadata

Field	Value
Publication number	US-10311184-B2
Application number	US-201715447010-A
Country	US
Kind code	B2
Filing date	Mar 1, 2017
Priority date	Mar 2, 2016
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

Example embodiments of disclosed configurations include a process (and system and non-transitory computer storage readable medium) for verifying an operation or a functionality of a design under test (DUT) through a distributed database processing system. In one or more embodiments, the emulator performs emulation of a DUT, and traces signals of the DUT based on the emulation. In one aspect, the traced signals are divided into multiple segments and are stored in the distributed database processing system in a form of key-value pairs. The distributed database processing system generates analysis segments based on corresponding segments of the traced signals and corresponding analysis rules. An analysis rule describes how to determine a particular characteristic of a corresponding segment of a signal. The distributed database processing system aggregates the analysis segments and generates a circuit analysis result indicating an aspect of the functionality of the DUT.

First claim

What is claimed is:

1. A method of verifying functionality of a design under test (DUT) for manufacture of an integrated circuit, the method comprising:
receiving, at a host system, from a hardware emulator comprising at least one field-programmable gate array (FPGA) configured to emulate the DUT, input waveform data including states of a signal of the DUT traced by the hardware emulator;
dividing, at the host system, the input waveform data into input waveform segments;
storing the input waveform segments at a distributed database processing system in communication with the host system;
generating analysis rules, each analysis rule associated with a corresponding one of the input waveform segments, each analysis rule describing how to determine a particular characteristic of a corresponding input waveform segment;
storing the analysis rules at the distributed database processing system, the distributed database processing system configured to map each input waveform segment to the corresponding analysis rule and generate analysis segments based on the input waveform segments and the corresponding analysis rules, each analysis segment indicating a characteristic of one or more corresponding input waveform segments; and
retrieving, at the host system, an analysis result from the distributed database processing system, the analysis result representing an aspect of the functionality of the DUT, the analysis result generated at the distributed database processing system based on the analysis segments.

2. The method of claim 1 , wherein each of the analysis segments is generated in a key-value pair.

3. The method of claim 1 , wherein each of the analysis rules is generated in a key-value pair.

4. The method of claim 1 , wherein the characteristic of one or more corresponding input waveform segments is a power consumption of the one or more corresponding input waveform segments, and wherein each analysis segment is stored as a key-value pair.

5. The method of claim 1 , wherein the characteristic of one or more corresponding input waveform segments is a number of toggles in the one or more corresponding input waveform segments, and wherein each analysis segment is stored as a key-value pair.

6. The method of claim 1 , wherein each of the analysis segments represents a number of toggles within a corresponding input waveform segment according to the analysis rule, the distributed database processing system configured to generate the analysis result indicating a peak power consumption of the DUT by (i) multiplying, for each of the analysis segments, the number of toggles with a corresponding coefficient to generate a corresponding power consumption value, and (ii) adding the power consumption values of the analysis segments.

7. The method of claim 1 , wherein each of the analysis segments represents a number of toggles within a corresponding input waveform segment according to the analysis rule, the distributed database processing system configured to generate the analysis result indicating an average power consumption of the DUT by (i) multiplying, for each of the analysis segments, the number of toggles with a corresponding coefficient to generate a corresponding power consumption value, and (ii) obtaining an average of the power consumption values of the analysis segments.

8. A non-transitory computer readable medium storing instructions for verifying a functionality of a design under test (DUT) corresponding to an integrated circuit, the instructions when executed by at least one processor causes the processor to:
receiving, at a host system, from a hardware emulator comprising at least one field-programmable gate array (FPGA) configured to emulate the DUT, input waveform data including states of a signal of the DUT traced by the hardware emulator;
divide, at the host system, the input waveform data for the DUT into input waveform segments;
store the input waveform segments at a distributed database processing system in communication with the host system;
generate analysis rules, each analysis rule associated with a corresponding one of the input waveform segments, each analysis rule describing how to determine a particular characteristic of a corresponding input waveform segment;
store the analysis rules at the distributed database processing system, the distributed database processing system configured to map each input waveform segment to the corresponding analysis rule and generate analysis segments based on the input waveform segments and the corresponding analysis rules, each analysis segment indicating a characteristic of one or more corresponding input waveform segments; and
retrieve, at the host system, an analysis result from the distributed database processing system, the analysis result representing an aspect of the functionality of the DUT, the analysis result generated at the distributed database processing system based on the analysis segments.

9. The non-transitory computer readable medium of claim 8 , wherein each of the analysis segments is generated in a key-value pair.

10. The non-transitory computer readable medium of claim 8 , wherein each of the analysis rules is generated in a key-value pair.

11. The non-transitory computer readable medium of claim 8 , wherein the characteristic of one or more corresponding input waveform segments is a power consumption of the one or more corresponding input waveform segments, and wherein each analysis segment is stored as a key-value pair.

12. The non-transitory computer readable medium of claim 8 , wherein the characteristic of one or more corresponding input waveform segments is a number of toggles in the one or more corresponding input waveform segments, and wherein each analysis segment is stored as a key-value pair.

13. The non-transitory computer readable medium of claim 8 , wherein each of the analysis segments represents a number of toggles within a corresponding input waveform segment according to the analysis rule, wherein the analysis result indicates a peak power consumption of the DUT, and wherein the instruction when executed by the processor to cause the processor to generate the analysis result indicating the peak power consumption of the DUT by (i) multiplying, for each of the analysis segments, the number of toggles with a corresponding coefficient to generate a corresponding power consumption value, and (ii) adding the power consumption values of the analysis segments.

14. The non-transitory computer readable medium of claim 8 , wherein each of the analysis segments represents a number of toggles within a corresponding input waveform segment according to the analysis rule, wherein the analysis result indicates an average power consumption of the DUT, and wherein the instruction when executed by the processor to cause the processor to generate the analysis result indicating the average power consumption of the DUT by (i) multiplying, for each of the analysis segments, the number of toggles with a corresponding coefficient to generate a corresponding power consumption value, and (ii) obtaining an average of the power consumption values of the analysis segments.

15. A system for verifying a functionality of a design under test (DUT) corresponding to an integrated circuit, the system comprising:
a processor; and
a memory comprising instructions executable by the processor, the instructions when executed by the processor cause the processor to:
receiving, at a host system, from a hardware emulator comprising at least one field-programmable gate array (FPGA) configured to emulate the DUT, input waveform data including states of a signal of the DUT traced

Assignees

• Synopsys Inc

Inventors

• Liu Tayung

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F16/2455

  Query execution · CPC title

• G06F16/2379

  Updates performed during online database operations; commit processing · CPC title

• G06F2111/02

  CAD in a network environment, e.g. collaborative CAD or distributed simulation · CPC title