Reconfigurable processor and timing control method thereof

Patent metadata

Field	Value
Publication number	US-10311017-B2
Application number	US-201815922511-A
Country	US
Kind code	B2
Filing date	Mar 15, 2018
Priority date	Mar 17, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

The present disclosure provides a reconfigurable processor and a timing control method thereof. The reconfigurable processor comprises a reconfigurable cell array (RCA) including a plurality of reconfigurable cells (RCs) and a control unit; the control unit is configured to generate and send a timing control information to the RCA; and the RCA is configured to execute an operation task according to the timing control information, wherein the RC in the RCA starts to execute an operation when receiving the timing control information, and delivers the timing control information to a next level of RC within the RCA according to a preset order after the operation is completed; and when the RCA completes the operation task corresponding to the timing control information, the RCA destroys the timing control information, wherein the operation task includes operations executed by each level of the RCs receiving the timing control information. According to embodiments of the present disclosure, the operation efficiency of the RCA is improved, thereby optimizing the performance of the processor.

First claim

What is claimed is:

1. A reconfigurable processor, wherein the reconfigurable processor comprises a reconfigurable cell array RCA including a plurality of reconfigurable cells RCs and a control unit including a reconfigurable configuration manager RCM and a reconfigurable schedule manager RSM, wherein
the RCM is configured to parse a configuration information and send a result of the parsing to the RCA to configure an operation function of at least a part of the RCs in the RCA;
the RSM is configured to receive the configuration information from the RCM, to generate timing control information according to the configuration information, and to send the timing control information including a token to the RCA; and
the RCA is configured to execute an operation task according to the timing control information, wherein an RC in the RCA starts to execute an operation when receiving the timing control information, and delivers the timing control information to a next level of RC within the RCA according to a preset order after the operation is completed; and when the RCA completes the operation task corresponding to the timing control information, the RCA destroys the timing control information, wherein the operation task includes operations executed by each level of the RCs receiving the timing control information.

2. The reconfigurable processor according to claim 1 , wherein
the RSM is further configured to stop generating the token and generate a first blocking signal when a blocking occurs in a memory MEM and/or an output first-in-first-out register OFIFO; and
the RCA is further configured to suspend a corresponding operation when the RC in the RCA receives the first blocking signal.

3. The reconfigurable processor according to claim 2 , wherein
the RCM is further configured to generate a second blocking signal when parsing of a clock cycle has not been completed at the time the clock cycle arrives; and
the RCA is further configured to suspend a corresponding operation when the RC in the RCA receives the second blocking signal.

4. The reconfigurable processor according to claim 3 , wherein
the RSM is further configured to stop generating the token when the RSM monitors that the RCM generates the second blocking signal.

5. The reconfigurable processor according to claim 2 , wherein
the RCM is further configured to switch the RC that has executed an operation corresponding to the timing control information to a configuration required for a next operation task when parsing of a clock cycle has been completed.

6. The reconfigurable processor according to claim 1 , wherein
the RCA is specifically configured to write an execution result of the operation task into OFIFO and/or MEM and destroy the timing control information by the RC that receives the timing control information last in the RCA, when the operation task corresponding to the timing control information is completed.

7. The reconfigurable processor according to claim 1 , wherein
the RSM is further configured to send a release signal of each level of the RCs to the RCM when an execution result of the RCA is obtained; and
the RCM is configured to switch each level of the RCs corresponding to the release signal to a configuration required for a next operation task when receiving the release signal.

8. The reconfigurable processor according to claim 1 , wherein
the RCA is further configured to turn off power and clock of an idle RC.

9. The reconfigurable processor according to claim 1 , wherein the preset order comprises that the timing control information is delivered from an upper level of RC to a lower level of RC in the RCA, or delivered arbitrarily between RCs of a same level in the RCA.

10. A timing control method of a reconfigurable processor, wherein the reconfigurable processor comprises a reconfigurable cell array RCA including a plurality of reconfigurable cells RCs and a control unit including a reconfigurable configuration manager RCM and a reconfigurable schedule manager RSM, and the method comprises:
parsing, by the RCM, a configuration information and sending, by the RCM, a result of the parsing to the RCA to configure an operation function of at least a part of the RCs in the RCA;
receiving, by the RSM, the configuration information from the RCM, generating, by the RSM, timing control information according to the configuration information, and sending, by the RSM the timing control information including a token to the RCA;
starting executing, by an RC in the RCA, an operation when receiving the timing control information, and delivering, by the RC in the RCA, the timing control information to a next level of RC within the RCA according to a preset order after the operation is completed; and
destroying, by the RCA, the timing control information, when the RCA completes an operation task corresponding to the timing control information, wherein the operation task includes operations executed by each level of the RCs receiving the timing control information.

11. The method according to claim 10 , wherein the method further comprises:
stopping generating, by the RSM, the token and generating, by the RSM, a first blocking signal when a blocking occurs in a memory MEM and/or an output first-in-first-out register OFIFO; and
suspending, by the RCA, a corresponding operation when the RC in the RCA receives the first blocking signal.

12. The method according to claim 11 , wherein the method further comprises:
generating, by the RCM, a second blocking signal when parsing of a clock cycle has not been completed at the time the clock cycle arrives; and
suspending, by the RCA, a corresponding operation when the RC in the RCA receives the second blocking signal.

13. The method according to claim 12 , wherein after the RCM generates the second blocking signal, the method further comprises:
stopping generating, by the RSM, the token when the RSM monitors that the RCM generates the second blocking signal.

14. The method according to claim 11 , wherein the method further comprises:
switching, by the RCM, the RC that has executed an operation corresponding to the timing control information to a configuration required for a next operation task when parsing of a clock cycle has been completed.

15. The method according to claim 10 , wherein destroying the timing control information comprises:
writing, by the RC that receives the timing control information last in the RCA, an execution result of the operation task into OFIFO and/or MEM and destroying, by the RC that receives the timing control information last in the RCA, the timing control information when the operation task corresponding to the timing control information is completed.

16. The method according to claim 10 , wherein after the RCA completes the operation task corresponding to the timing control information, the method further comprises:
sending, by the RSM, a release signal of each level of the RCs to the RCM when execution result of the RCA is obtained; and
switching, by the RCM, each level of the RCs corresponding to the release signal to a configuration required for a next operation task when receiving the release signal.

17. The method according to claim 10 , wherein the method further comprises:
turning off, by the RCA, power and clock of an idle RC.

18. The method according to claim 10 , wherein the preset order comprises that the timing control information is delivered from an upper level of RC to a lower level of RC, or delivered arbitrarily between RCs of a same level in the RCA.

Assignees

• Univ Tsinghua

Inventors

• Liu Leibo
• Wu Youyu
• Wei Shaojun

Classifications

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F15/76 Primary

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F15/7871 Primary

  Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS · CPC title

• G06F15/7892 Primary

  Reconfigurable logic embedded in CPU, e.g. reconfigurable unit · CPC title

• G06F15/7817

  Specially adapted for signal processing, e.g. Harvard architectures · CPC title