Systems and methods for input/output computing resource control

Patent metadata

Field	Value
Publication number	US-10310974-B2
Application number	US-201515755414-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.

First claim

What is claimed is:

1. A host device, comprising:
a processor;
logic coupled with the processor, to: identify a tag identifier (Tag ID) for a process or container of the host device, wherein the Tag ID identifies a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, the outbound transaction to be conducted by the process or container; and map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor, wherein the process or container is to use the PASID to conduct the outbound transaction via the identified queue pair.

2. The host device of claim 1 , wherein the logic is to:
identify the queue pair as an unused queue pair from a pool of queue pairs;
generate the Tag ID associated with the identified queue pair; and
cause storage of the Tag ID for the queue pair in a register of the host device.

3. The host device of claim 2 , wherein the outbound transaction comprises a request to access a memory associated with the hardware device, wherein the logic is to:
receive the memory access request;
determine whether the memory access request includes the Tag ID; and
based on a result of the determination, provide the Tag ID to second logic.

4. The host device of claim 3 , wherein the Tag ID comprises a namespace identifier associated with the memory request.

5. The host device of claim 4 , wherein the logic is to:
determine whether the queue pair is enabled with PASID capability; and
based on a result of the determination,
include the Tag ID in a PASID field in a Transaction Layer Packet (TLP) prefix; and
generate a transaction to the queue pair in accordance with the memory request and in association with the PASID TLP prefix, to cause the transaction to be performed by the process or container using the queue pair.

6. The host device of claim 5 , wherein the transaction is a Peripheral Component Interconnect Express (PCIe) transaction, and wherein the hardware device is a PCIe device.

7. The host device of claim 5 , wherein the logic is first logic, wherein the host device further comprises the second logic coupled with the processor to:
set a PASID enable indicator of a per-queue PASID register of the hardware device to enable the hardware device to perform the transaction using the queue pair;
use the namespace identifier to set the per-queue PASID register; and
re-initialize the queue pair to be used in the transaction.

8. The host device of claim 7 , further comprising third logic coupled with the processor to store PASIDs associated with inbound transactions between the hardware device and the processor in a PASID repository, wherein the third logic is to retrieve the PASID from the PASID repository.

9. A hardware device, comprising:
logic to perform privilege check for an outbound transaction initiated by a host device and associated with a Process Address Space Identifier (PASID) that indicates a queue pair of the hardware device, wherein the PASID is a PASID of a process or container of the host device associated with the outbound transaction, wherein to perform the privilege check includes to compare the PASID with PASID values stored in a per-queue PASID register of the hardware device, and to allow the outbound transaction based at least in part on a result of the comparison.

10. The hardware device of claim 9 , wherein the logic is to, prior to the comparison of the PASID associated with the queue pair with PASID values stored in the per-queue PASID register:
determine that a PASID Extended Capability indicator of a PASID Extended Capability register is set; and
determine that a PASID Enabled indicator of the per-queue PASID register associated with the queue pair is set,
wherein the PASID Extended Capability register provides for enablement of outbound transactions, and wherein the outbound transactions comprise Peripheral Component Interconnect Express (PCIe) transactions, and wherein the hardware device is an input-output (I/O) PCIe device.

11. The hardware device of claim 10 , wherein the PASID is included in a Transaction Layer Packet (TLP) prefix, wherein the PASID Extended Capability indicator indicates a capability of the hardware device to perform outbound transactions associated with the PASID TLP prefix.

12. The hardware device of claim 9 , wherein the logic is to receive the PASID from the host device.

13. A method for utilizing resources of a hardware device of a host device, comprising:
identifying, by the host device, a tag identifier (Tag ID) for a process or container of the host device, wherein the Tag ID identifies a queue pair of a hardware device of the host device for an outbound transaction between the processor and the hardware device, the outbound transaction to be conducted by the process or container; and
mapping, by the host device, the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction between the hardware device and the processor, to enable the outbound transaction by the process or container via the identified queue pair.

14. The method of claim 13 , further comprising:
identifying, by the host device, the queue pair as an unused queue pair from a pool of queue pairs;
generating, by the host device, the Tag ID associated with the identified queue pair; and
causing, by the host device, storage of the Tag ID for the queue pair in a register of the host device.

15. The method of claim 14 , wherein the outbound transaction comprises a request to access a memory associated with the hardware device, wherein the method further comprises:
receiving, by the host device, the memory access request; and
determining, by the host device, whether the memory access request includes the Tag ID, wherein the Tag ID comprises a namespace identifier associated with the memory request.

16. The method of claim 15 , further comprising:
determining, by the host device, whether the queue pair is PASID-enabled; and
based on a result of the determination,
including, by the host device, the PASID in a Transaction Layer Packet (TLP) prefix; and
generating, by the host device, a transaction to the queue pair in accordance with the memory request and in association with the PASID TLP prefix, to perform the transaction using the queue pair.

17. The method of claim 16 , further comprising:
setting, by the host device, a PASID Enabled indicator of a per-queue PASID register of the hardware device to enable the hardware device to perform the transaction using the queue pair;
using, by the host device, the namespace identifier to set the per-queue PASID register; and
re-initializing, by the host device, the queue pair to be used in the transaction.

18. The method of claim 14 , further comprising:
retrieving, by the host device, the PASID from a PASID repository associated with the host device.

19. A method for utilizing resources of a hardware device of a host device, comprising:
comparing, by the hardware device of the host device, a Process Address Space Identifier (PASID) that indicates a queue pair of the hardware device, with PASID values stored in a per-queue PASID register of the hardware device, wherein the PASID is a PASID of a process or container of the host device associated with an outbound transaction; and
performing or causing to be performed, by the hardware device, the outbound transaction based at least in part on a result of the comparison.

20. The method

Assignees

• Intel Corp

Inventors

• Liang Cunming
• Verplank Edwin
• Cohen David E
• Zhou Danny

Classifications

• G06F13/20

  for access to input/output bus · CPC title

• G06F21/85 Primary

  interconnection devices, e.g. bus-connected or in-line devices · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title