Method and device for generating configuration information of dynamic reconfigurable processor

Patent metadata

Field	Value
Publication number	US-10310894-B2
Application number	US-201415119114-A
Country	US
Kind code	B2
Filing date	Jun 16, 2014
Priority date	Mar 31, 2014
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

Provided is a method for generating configuration information of a dynamic reconfigurable processor. The dynamic reconfigurable processor includes a processing unit array, and the processing unit array includes a plurality of processing units. The method includes steps of: reading information of a task to be executed and generating an array configuration information top of the processing unit array according to the information; generating a plurality of processing unit configuration information corresponding to the plurality of processing units respectively according to the information; and assembling the array configuration information top and the plurality of processing unit configuration information.

First claim

What is claimed is:

1. A method for generating configuration information of a dynamic reconfigurable processor, the dynamic reconfigurable processor comprising a processing unit array, and the processing unit array including a plurality of processing units, wherein the method comprises steps of:
reading information of a task to be executed and generating an array configuration information top of the processing unit array according to the information;
generating a plurality of processing unit configuration information corresponding to the plurality of processing units respectively according to the information; and
assembling the array configuration information top and the plurality of processing unit configuration information;
wherein generating the array configuration information top of the processing unit array according to the information comprises:
extracting a computational granularity and a number of loop iteration of the task to be executed from the information, and the array configuration information top comprises the computational granularity and the number of loop iteration;
wherein the processing unit configuration information includes processing unit configuration information top and a plurality of operator configuration information, the processing unit configuration information top includes an initial machine cycle number, an operator number and a configuration change option, and the operator configuration information includes an input, an ALU operation code, a continuous operation cycle number, an interval cycle number and a memory write access.

2. The method according to claim 1 , wherein generating a plurality of processing unit configuration information corresponding to the plurality of processing units respectively according to the information comprises:
determining an execution instruction mapped into one of the plurality of processing units according to the information, and
generating the processing unit configuration information corresponding to the one processing unit according to the execution instruction.

3. The method according to claim 1 , wherein a number of the operator configuration information is substantially the same as the operator number, and each operator has corresponding operator configuration information.

4. The method according to claim 1 , wherein assembling the array configuration information top and the plurality of processing unit configuration information comprises:
assembling the array configuration information top and the plurality of processing unit configuration information in a preset order.

5. A device for generating configuration information of a dynamic reconfigurable processor, the dynamic reconfigurable processor comprising a processing unit array, and the processing unit array including a plurality of processing units, wherein the device comprises:
a storage module of a task to be executed, configured to store information of the task to be executed;
a reading module, configured to read the information;
a first generating module, configured to generate array configuration information top of the processing unit array according to the information;
a second generating module, configured to generate a plurality of processing unit configuration information corresponding to the plurality of processing units respectively according to the information; and
an assembly module, configured to assemble the array configuration information top and the plurality of processing unit configuration information to generate the configuration information of the dynamic reconfigurable processor,
wherein the first generating module is configured to extract a computational granularity and a number of loop iteration of the task to be executed from the information, and the array configuration information top comprises the computational granularity and the number of loop iteration,
wherein the processing unit configuration information includes the processing unit configuration information top and a plurality of operator configuration information, the processing unit configuration information top includes an initial machine cycle number, an operator number and a configuration change option, and the operator configuration information includes an input, an ALU operation code, a continuous operation cycle number, an interval cycle number and a memory write access.

6. The device according to claim 5 , wherein the second generating module is configured to determine an execution instruction mapped into one of the plurality of processing units according to the information, and to generate the processing unit configuration information corresponding to the one processing unit according to the execution instruction.

7. The device according to claim 5 , wherein a number of the operator configuration information is substantially the same as the operator number, and each operator has corresponding operator configuration information.

8. The device according to claim 5 , further comprising:
a configuration storage module, configured to store the configuration information generated by the assembly module.

9. A processor configuration device, comprising:
a first configuration module, configured to read array configuration information top of configuration information, the read array configuration information top comprising a computational granularity and a number of loop iteration extracted from information of the task to be executed and to distribute the computational granularity and the number of loop iteration of the array configuration information top to a processing unit array;
a second configuration module, configured to read a plurality of processing unit configuration information in the configuration information, and to distribute the plurality of processing unit configuration information to corresponding processing units respectively, wherein the processing unit configuration information includes processing unit configuration information top and a plurality of operator configuration information, the processing unit configuration information top includes an initial machine cycle number, an operator number and a configuration change option, and the operator configuration information includes an input, an ALU operation code, a continuous operation cycle number, an interval cycle number and a memory write access; and
a configuration controlling module, configured to control the first configuration module to read the array configuration information top according to operating parameters, and to control the second configuration module to read the plurality of processing unit configuration information according to the operating parameters.

10. The device according to claim 9 , wherein the operating parameters include a count of an initial machine cycle number, a count of a continuous cycle number, a count of an interval cycle number, a count of an operator number and a count of a number of loop iteration.

11. The device according to claim 9 , wherein the second configuration module comprises:
a first configuration unit, configured to read the processing unit configuration information in the plurality of processing unit configuration information, and to distribute the processing unit configuration information top to corresponding processing units respectively, wherein the processing unit configuration information top includes an initial machine cycle number;
a second configuration unit, configured to read first operator configuration information in the plurality of processing unit configuration information respectively when a count of the initial machine cycle number is finished, and to distribute the first operator configuration information to corresponding processing units re

Assignees

• Univ Tsinghua

Inventors

• Liu Leibo
• Wang Yansheng
• Peng Guiqiang
• Li Zhaoshi
• Yin Shouyi
• Wei Shaojun

Classifications

• G06F15/7871 Primary

  Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS · CPC title

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title