Display panel and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10304871-B2
Application number	US-201815869160-A
Country	US
Kind code	B2
Filing date	Jan 12, 2018
Priority date	Dec 30, 2016
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

A display panel and a manufacturing method are provided. The display panel includes a substrate, multiple active switches disposed on the substrate and a low dielectric constant protective layer. The low dielectric constant protective layer is formed on the numerous active switches. A relative dielectric constant of the low dielectric constant protective layer is smaller than a relative dielectric constant of silicon nitride.

First claim

What is claimed is:

1. A display panel comprising:
a substrate;
a plurality of active switches, disposed on the substrate;
a low dielectric constant protective layer formed on the plurality of active switches, wherein a relative dielectric constant of the low dielectric constant protective layer is lower than a relative dielectric constant of silicon nitride;
wherein the low dielectric constant protective layer comprises a mesoporous silica; the mesoporous silica comprises a plurality of hollow columnar sub-components connected with each other, a cross section of the sub-component is hexagonal, and a middle of the sub-component has a circular through hole; the mesoporous silica comprises a plurality of sub-elements, the sub-element comprises the sub-components arranged in three lines, an intermediate line of the sub-element comprises three sub-components arranged abreast, a first line and a third line of the sub-element each comprise two sub-components arranged abreast, the two sub-components of each of the first line and the third line each are disposed between any two sub-components of the three sub-components in the intermediate line;
wherein a plurality of first-layer wires are disposed on the substrate, an insulating dielectric layer is disposed on the first-layer wires, an amorphous silicon layer is disposed on the insulating dielectric layer and corresponding to a gate wire section of the first-layer wires, an ohmic contact layer is disposed on and corresponding to the amorphous silicon layer, a source wire section and a drain wire section are separated from each other and disposed on the ohmic contact layer, a groove is defined between the source wire section and the drain wire section, the groove passes through the ohmic contact layer, a bottom of the groove is the amorphous silicon layer, a width of the source wire section and the drain wire section as a whole is larger than a width of the amorphous silicon layer, the low dielectric constant protective layer is disposed on the source wire section and the drain wire section, a pixel electrode layer is disposed on the low dielectric constant protective layer, the low dielectric constant protective layer is defined with a via hole corresponding to the drain wire section, the pixel electrode layer is connected with the drain wire section by the via hole; a side of a portion of the source wire section beyond the amorphous silicon layer is immediately connected with the insulating dielectric layer, an opposite side of the portion of the source wire section is immediately connected with the low dielectric constant protective layer, and a section of the insulating dielectric layer corresponding to the via hole is connected with the drain wire section.

2. A display panel comprising:
a substrate;
a plurality of active switches, disposed on the substrate;
a low dielectric constant protective layer, formed on the plurality of active switches, wherein a relative dielectric constant of the low dielectric constant protective layer is lower than a relative dielectric constant of silicon nitride,
wherein a plurality of first-layer wires are disposed on the substrate, an insulating dielectric layer is disposed on the first-layer wires, an amorphous silicon layer is disposed on the insulating dielectric layer and corresponding to a gate wire section of the first-layer wires, an ohmic contact layer is disposed on and corresponding to the amorphous silicon layer, a source wire section and a drain wire section are separated from each other and disposed on the ohmic contact layer, a groove is defined between the source wire section and the drain wire section, the groove penetrates through the ohmic contact layer, a bottom of the groove is the amorphous silicon layer, a width of the source wire section and the drain wire section as a whole is larger than a width of the amorphous silicon layer, the low dielectric constant protective layer is disposed on the source wire section and the drain wire section, a pixel electrode layer is disposed on the low dielectric constant protective layer, the low dielectric constant protective layer is defined with a via hole corresponding to the drain wire section, the pixel electrode layer is connected to the drain wire section by the via hole.

3. The display panel according to claim 2 , wherein a side of a portion of the source wire section beyond the amorphous silicon layer is immediately connected with the insulating dielectric layer, and an opposite side of the portion of the source wire section is immediately connected with the low dielectric constant protective layer, and a section of the insulating dielectric layer corresponding to the via hole is immediately connected with the drain wire section.

4. The display panel according to claim 2 , wherein the relative dielectric constant of the low dielectric constant protective layer is lower than that of silicon oxide.

5. The display panel according to claim 2 , wherein a material of the low dielectric constant protective layer comprises nanoporous silicon.

6. The display panel according to claim 2 , wherein a dielectric constant of the insulating dielectric layer is larger than that of silicon oxide and is larger than that of silicon nitride.

7. The display panel according to claim 2 , wherein the low dielectric constant protective layer comprises a mesoporous silica.

8. The display panel according to claim 7 , wherein a relative dielectric constant of the mesoporous silica is in the range of 1.4˜2.4.

9. The display panel according to claim 7 , wherein the mesoporous silica comprises a plurality of hollow columnar sub-components connected with each other, a cross section of the sub-component is hexagonal, and a middle of the sub-component has a circular through hole.

10. The display panel according to claim 9 , wherein the mesoporous silica comprises a plurality of sub-elements, the sub-element comprises the sub-components arranged in three lines, an intermediate line of the sub-element comprises three sub-components arranged abreast, a first line and a third line of the sub-element each comprise two sub-components arranged abreast, the two sub-components of each of the first line and the third line each are disposed between any two sub-components of the three sub-components in the intermediate line.

11. The display panel according to claim 9 , wherein the mesoporous silica comprises a plurality of sub-elements, each of the plurality of sub-elements comprises seven sub-components, one of which is surrounded and connected by the other six sub-components.

12. A manufacturing method of a display panel, comprising steps of:
arranging a plurality of active switches on a substrate; and
forming a low dielectric constant protective layer with a relative dielectric constant lower than a relative dielectric constant of silicon nitride on the plurality of active switches;
wherein in the step of arranging a plurality of active switches on a substrate, a plurality of first-layer wires are disposed on the substrate, an insulating dielectric layer is disposed on the plurality of first-layer wires, an amorphous silicon layer is disposed on the insulating dielectric layer and corresponding to a gate wire section of the first-layer wires, an ohmic contact layer is disposed on and corresponding to the amorphous silicon layer, a source wire section and a drain wire section are separated from each other and disposed on the ohmic contact layer, a groove is defined between the source wire section and the drain wire section, the groove penetrates through the ohmic contact layer, a bottom of the groove is the amorphous silicon layer, a width of the source wire section and the drain wire

Assignees

• Hkc Corp Ltd
• Chongqing Hkc Optoelectronics Tech Co Ltd

Inventors

• Cho En-Tsung
• Fan Kun
• Tian Yiqun

Classifications

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• G02F2201/50

  Protective arrangements · CPC title

• G02F2202/42

  Materials having a particular dielectric constant · CPC title

• G02F2202/103

  a-Si · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title