Memory device and method of operating the same to prevent occurrence of read fail by adjusting bit line voltage

Patent metadata

Field	Value
Publication number	US-10304542-B2
Application number	US-201715613649-A
Country	US
Kind code	B2
Filing date	Jun 5, 2017
Priority date	Aug 29, 2016
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

A memory device includes a memory block including a plurality of stacked sub-memory blocks, peripheral circuits configured to perform program, read and erase operations on the memory block or on a block selected from among the sub-memory blocks, and a control logic configured to control the peripheral circuits so that, during a read operation on the memory block, if a block on which a partial erase operation has been performed is not present among the sub-memory blocks, voltages to be used for the read operation are set and so that, if a block on which the partial erase operation has been performed is present among the sub-memory blocks, the voltages to be used for the read operation are varied depending on a position of a sub-memory block that is a target of the read operation.

First claim

What is claimed is:

1. A memory device, comprising:
a memory block including a plurality of sub-memory blocks;
a peripheral circuit configured to perform at least one of program, read and erase operations on the memory block or on a sub-memory block selected from among the sub-memory blocks; and
a control logic configured to:
control the peripheral circuit in a read operation on the memory block to set at least one bit line voltage for precharging to be used for the read operation,
to determine whether a sub-memory block on which a partial erase operation has been performed is present among the sub-memory blocks, wherein all memory cells in the sub-memory block on which the partial erase operation has been performed are erased,
wherein depending upon the determination the control logic changes the at least one bit line voltage for precharging depending on a position of a target sub-memory block for the read operation, and
wherein the control logic controls the peripheral circuit so that, as a sequential position of the partially erased sub-memory block, in a program operation sequence leads those of other sub-memory blocks, the at least one bit line voltage for precharging to be used for the read operation is decreased.

2. The memory device according to claim 1 , wherein the control logic controls the peripheral circuit so that the target sub-memory block is other than the partially erased sub-memory block.

3. The memory device according to claim 1 , wherein the control logic controls the peripheral circuit so that, as the target sub-memory block is located at a relatively higher sequential position, the at least one bit line voltage for precharging is lower.

4. The memory device according to claim 1 , wherein the peripheral circuit comprises:
a voltage generation circuit configured to generate operating voltages required for various operations;
a row decoder configured to transfer the operating voltages to the memory block; and
a page buffer unit configured to apply bit line voltages to bit lines coupled to the memory block or to sense data in memory cells included in the memory block.

5. The memory device according to claim 4 , wherein the page buffer unit is configured to adjust turn-on voltages for switches that transfer the bit line voltages to the bit lines.

6. The memory device according to claim 5 , wherein the turn-on voltages are voltages applied to gates of the switches.

7. The memory device according to claim 5 , wherein the bit line voltages are proportional to the turn-on voltages.

8. The memory device according to claim 1 , wherein each of the sub-memory blocks comprises a normal memory block and a flag block.

9. The memory device according to claim 8 , wherein:
the normal memory block stores user data, and
the flag block stores data related to the memory device.

10. The memory device according to claim 9 , wherein the flag block stores data related to whether the partial erase operation has been performed on the memory block and data related to the partially erased sub-memory block.

11. A method for operating a memory device, comprising:
setting a bit line voltage;
determining whether a partially erased sub-memory block is present among sub-memory blocks included in a selected memory block;
maintaining the bit line voltage if a partially erased sub-memory block is not present;
maintaining the bit line voltage or setting a bit line voltage having a level lower than that of the bit line voltage depending on a position of a target sub-memory block for a read operation if the partially erased sub-memory block is present; and
performing the read operation using one of the maintained bit line voltage and the set bit line voltage,
wherein the bit line voltage is decreased as the target sub-memory block is located at a relatively higher sequential position.

12. The method according to claim 11 , wherein the determining whether the partially erased sub-memory block is present in the selected memory block comprises determining whether the partially erased sub-memory block is present in the selected memory block based on data stored in a flag block included in the selected memory block.

13. The method according to claim 11 , further comprising, if the partially erased sub-memory block is not present, performing the read operation using the bit line voltage that is set before determining whether the partially erased sub-memory block is present.

14. The method according to claim 11 , wherein the bit line voltage is applied to bit lines coupled to the memory block to precharge the bit lines during a read operation of the memory block.

15. The method according to claim 11 , further comprising setting the bit line voltage depending on a number of sub-memory blocks on which a partial erase operation has been performed when the bit line voltage is set.

16. A method for performing a read operation on at least one sub-memory block selected from among sub-memory blocks in a memory device, the method comprising:
applying a first bit line voltage;
maintaining the first bit line voltage or re-applying a second bit line voltage that becomes lower than the first bit line voltage, depending on a number of at least one partially erased sub-memory block and a position of a target sub-memory block for a read operation if the partially erased sub-memory block is present among the sub-memory blocks; and
performing the read operation on the selected sub-memory block using the first bit line voltage or the second bit line voltage,
wherein the second bit line voltage is decreased as the number of the partially erased sub-memory block is larger and the target sub-memory block is located at a relatively higher sequential position.

Assignees

• Sk Hynix Inc

Inventors

• Lim Sung Yong
• Baek Seung Hwan
• Shin Yeon Ji

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title