Secure crypto module including optical glass security layer

US10303639B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10303639-B2
Application numberUS-201815862104-A
CountryUS
Kind codeB2
Filing dateJan 4, 2018
Priority dateMar 24, 2016
Publication dateMay 28, 2019
Grant dateMay 28, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of fabricating a printed circuit board (PCB) is presented. The PCB includes a glass security layer. The method includes forming the glass security layer upon a PCB wiring layer. The method includes optically attaching an optical electromagnetic radiation (EM) emitter upon the glass security layer. The method includes optically attaching an optical EM receiver upon the glass security layer. The method further includes electrically connecting an optical monitor device to the optical EM receiver.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating a printed circuit board (PCB) comprising a glass security layer, the method comprising: forming the glass security layer upon a PCB wiring layer; optically attaching an optical electromagnetic radiation (EM) emitter upon the glass security layer; optically attaching an optical EM receiver upon the glass security layer; electrically connecting an optical monitor device to the optical EM receiver; electrically connecting the optical monitor device to a destruct feature within the crypto component, wherein the destruct feature is programmed when the optical EM receiver detects that an interference pattern of optical EM emitted from the optical EM emitter and transmitted by the glass security layer is different from a predetermined expected optical EM interference pattern. 2. The method of claim 1 , further comprising: forming an optically opaque encapsulation layer upon the glass security layer, upon the optical EM emitter, and upon the optical EM receiver. 3. The method of claim 1 , further comprising: electrically connecting the optical monitor device to the optical EM emitter. 4. The method of claim 2 , wherein the optically opaque encapsulation layer is formed to a thickness greater than respective heights of the optical EM emitter and the optical EM receiver. 5. The method of claim 1 , further comprising: electrically attaching a crypto component to a wire of the PCB. 6. The method of claim 1 , wherein the destruct feature is programmed when the optical EM receiver detects a predetermined threshold decrease of optical flux of optical EM transmitted from the optical EM emitter to the optical EM receiver by the glass security layer.

Assignees

Inventors

Classifications

  • for fault attacks · CPC title

  • Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

  • Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups H04B10/03 - H04B10/70, e.g. optical power feeding or optical transmission through water · CPC title

  • Electrical coupling · CPC title

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What does patent US10303639B2 cover?
A method of fabricating a printed circuit board (PCB) is presented. The PCB includes a glass security layer. The method includes forming the glass security layer upon a PCB wiring layer. The method includes optically attaching an optical electromagnetic radiation (EM) emitter upon the glass security layer. The method includes optically attaching an optical EM receiver upon the glass security la…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F13/4068. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 28 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).