Digital filter with a pipeline structure operating in multiple clock domains, and a corresponding device

Patent metadata

Field	Value
Publication number	US-10303201-B2
Application number	US-201715478638-A
Country	US
Kind code	B2
Filing date	Apr 4, 2017
Priority date	Jul 8, 2014
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.

First claim

The invention claimed is:

1. A digital filter, comprising:
a first filter module operating with a first clock signal on first signal samples;
a second filter module operating with a second clock signal on second signal samples, wherein a frequency of the second clock signal is different from a frequency of the first clock signal;
a first re-sampling module having an input coupled to an output of the first filter module and an output coupled to an input of the second filter module, said first re-sampling module comprising:
up-sampling and down-sampling buffers activatable in response to said first and second filter modules operating at different clock frequencies,
wherein said up-sampling and down-sampling buffers are configured to convert signal samples between the frequency of the first clock signal and the frequency of the second clock signal.

2. The digital filter of claim 1 , further comprising a phase generator configured to align processing of signal samples with respect to the first and second filter modules and first re-sampling module.

3. The digital filter of claim 2 , wherein said phase generator is a centralized phase generator configured to distribute a single phase alignment signal to the first and second filter modules and the first re-sampling module.

4. The digital filter of claim 2 , wherein said phase generator is a distributed phase generator with each of the first and second filter modules and the first re-sampling module operating in response to a dedicated phase alignment signal.

5. The digital filter of claim 4 , wherein the dedicated phase alignment signal for the first filter module is passed with signal samples to the first re-sampling module, and wherein the dedicated phase alignment signal for the first re-sampling module is passed with signal samples to the second filter module.

6. The digital filter of claim 1 , further comprising a second re-sampling module having an input coupled to an output of the second filter module and an output coupled to an input of the first filter module, said second re-sampling module comprising:
up-sampling and down-sampling buffers activatable in response to said first and second filter modules operating at different clock frequencies,
wherein said up-sampling and down-sampling buffers are configured to convert signal samples between the frequency of the first clock signal and the frequency of the second clock signal.

7. The digital filter of claim 6 , further comprising a summation module configured to sum input signal samples with signal samples output from the second re-sampling module to generate the first signal samples for input to the first filter module.

8. A digital filter, comprising:
a first memory including a first plurality of memory modules rotatable in response to a first clock at a first frequency and configured to receive first signal samples and output second signal samples;
a down-sampling buffer having an input coupled to an output of the first memory and configured to down-sample the second signal samples to generate third signal samples;
a second memory including a second plurality of memory modules rotatable in response to a second clock at a second frequency and configured to receive fourth signal samples derived from said third signal samples and output fifth signal samples;
an up-sampling buffer having an input coupled to an output of the second memory and configured to up-sample the fifth signal samples to generate sixth signal samples; and
a summation module configured to sum said sixth signal samples with input signal samples to generate said first signal samples.

9. The digital filter of claim 8 , further comprising a phase generator configured to align processing of signal samples with respect to the first and second memories, the down-sampling buffer and the up-sampling buffer.

10. The digital filter of claim 9 , wherein said phase generator is a centralized phase generator configured to distribute a single phase alignment signal to the first and second memories, the down-sampling buffer and the up-sampling buffer.

11. The digital filter of claim 10 , wherein said phase generator is a distributed phase generator with each of the first and second filter memories, the down-sampling buffer and the up-sampling buffer operating in response to a dedicated phase alignment signal.

12. The digital filter of claim 11 , wherein each dedicated phase alignment signal is passed with output signal samples.

13. A digital filter, comprising:
a first memory including a first plurality of memory modules rotatable in response to a first clock at a first frequency and configured to receive first signal samples and output second signal samples;
a down-sampling buffer having an input coupled to an output of the first memory and configured to generate third signal samples from said second signal samples;
a second memory including a second plurality of memory modules rotatable in response to a second clock at a second frequency and configured to receive the third signal samples and output fourth signal samples; and
an up-sampling buffer having an input coupled to an output of the second memory and configured to generate fifth signal samples;
wherein the first signal samples are derived from input signal samples and the fifth signal samples.

14. The digital filter of claim 13 , further comprising a phase generator configured to align processing of signal samples with respect to the first and second memories, the down-sampling buffer and the up-sampling buffer.

15. The digital filter of claim 14 , wherein said phase generator is a centralized phase generator configured to distribute a single phase alignment signal to the first and second memories, the down-sampling buffer and the up-sampling buffer.

16. The digital filter of claim 15 , wherein said phase generator is a distributed phase generator with each of the first and second memories, the down-sampling buffer and the up-sampling buffer operating in response to a dedicated phase alignment signal.

17. The digital filter of claim 16 , wherein each dedicated phase alignment signal is passed with output signal samples.

18. The digital filter of claim 6 , wherein the first signal samples are derived from input signal samples and the signal samples output from the second re-sampling module.

Assignees

• St Microelectronics Srl

Inventors

• Pirozzi Francesco

Classifications

• H03H2220/04

  Pipelined · CPC title

• H03H17/0292 Primary

  Time multiplexed filters; Time sharing filters · CPC title

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title