Methods of forming semiconductor devices including conductive contacts on source/drains

Patent metadata

Field	Value
Publication number	US-10297673-B2
Application number	US-201514878230-A
Country	US
Kind code	B2
Filing date	Oct 8, 2015
Priority date	Oct 8, 2014
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate structure crossing over the plurality of fin-shaped channels and forming a source/drain adjacent a side of the gate structure. The source/drain may cross over the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The methods may also include forming a metallic layer on an upper surface of the source/drain and forming a conductive contact on the metallic layer opposite the source/drain. The conductive contact may have a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising:
forming a plurality of fin-shaped channels on a substrate;
forming a gate structure crossing over the plurality of fin-shaped channels;
forming a source/drain adjacent a side of the gate structure, the source/drain crossing over the plurality of fin-shaped channels and being electrically connected to the plurality of fin-shaped channels;
forming a metallic layer on an upper surface of the source/drain; and
forming a conductive contact on the metallic layer opposite the source/drain, the conductive contact having a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer.

2. The method of claim 1 , wherein forming the metallic layer comprises:
forming an insulation layer on the gate structure and the source/drain;
forming an opening extending through the insulation layer and exposing at least a portion of the source/drain; and
forming the metallic layer on the source/drain.

3. The method of claim 2 , wherein the second length of the metallic layer in the longitudinal direction of the metallic layer is greater than a distance between two adjacent ones of the plurality of fin-shaped channels.

4. The method of claim 2 , wherein the insulation layer comprises a first insulation layer, and
wherein forming the gate structure comprises:
forming a dummy gate structure crossing over the plurality of fin-shaped channels;
forming a second insulation layer on sides of the dummy gate structure; and
replacing the dummy gate structure with a gate insulation layer and a gate electrode, the gate electrode comprising a metal.

5. The method of claim 2 , wherein the insulation layer comprises a first insulation layer, and
wherein forming the conductive contact comprises:
forming a second insulation layer on the metallic layer in the opening;
forming a contact opening extending through the second insulation layer and exposing the metallic layer; and
forming the conductive contact in the contact opening.

6. The method of claim 1 , wherein the metallic layer comprises a silicide layer and/or a stack of layers, and
wherein the stack of layers comprises a stack comprising a dielectric layer and a metal layer or a stack comprising a rare-earth or alkaline earth metal layer, a metal layer and a capping layer.

7. The method of claim 1 , wherein forming the source/drain and the metallic layer comprises:
forming an insulation layer on the plurality of fin-shaped channels and the gate structure;
forming an opening extending through the insulation layer and exposing the plurality of fin-shaped channels;
forming the source/drain in the opening by performing a epitaxial growth process using the plurality of fin-shaped channels that are exposed by the opening as seed layers; and
forming the metallic layer on the source/drain.

8. A method of forming a semiconductor device comprising:
forming a plurality of fin-shaped channels on a substrate;
forming a gate structure crossing over the plurality of fin-shaped channels;
forming a source/drain adjacent a side of the gate structure, the source/drain crossing over the plurality of fin-shaped channels and being electrically connected to the plurality of fin-shaped channels;
forming a metallic layer on an upper surface of the source/drain; and
forming a conductive contact on the metallic layer opposite the source/drain, the conductive contact vertically overlapping less than all of the plurality of fin-shaped channels.

9. The method of claim 8 , wherein the metallic layer vertically overlaps a first number of the plurality of fin-shaped channels that is greater than a second number of the plurality of fin-shaped channels that the conductive contact vertically overlaps.

10. The method of claim 9 , wherein the metallic layer vertically overlaps all of the plurality of fin-shaped channels.

11. The method of claim 8 , wherein the conductive contact vertically overlaps only a portion of the metallic layer in a longitudinal direction of the metallic layer.

12. The method of claim 8 , wherein forming the metallic layer and the conductive contact comprises:
forming a first insulation layer on the gate structure and the source/drain;
forming an opening extending through the first insulation layer and exposing the source/drain;
forming the metallic layer on the source/drain;
forming a second insulation layer on the metallic layer in the opening;
forming a contact opening extending through the second insulation layer and exposing the metallic layer; and
forming the conductive contact in the contact opening.

13. The method of claim 12 , wherein forming the gate structure comprises:
forming a dummy gate structure crossing over the plurality of fin-shaped channels;
forming a third insulation layer on sides of the dummy gate structure; and
replacing the dummy gate structure with a gate insulation layer and a gate electrode, the gate electrode comprising a metal.

14. The method of claim 8 , wherein the metallic layer comprises a silicide layer and/or a stack of layers, and
wherein the stack of layers comprises a stack comprising a dielectric layer and a metal layer or a stack comprising a rare-earth or alkaline earth metal layer, a metal layer and a capping layer.

15. A method of forming a semiconductor device comprising:
forming a plurality of fin-shaped channels on a substrate;
forming a gate structure crossing over the plurality of fin-shaped channels;
forming a source/drain adjacent a side of the gate structure, the source/drain crossing over the plurality of fin-shaped channels and being electrically connected to the plurality of fin-shaped channels; and
forming a conductive contact on an upper surface of the source/drain, the conductive contact having a first length in a longitudinal direction of the source/drain that is less than a second length of the source/drain in the longitudinal direction of the source/drain.

16. The method of claim 15 , wherein the conductive contact vertically overlaps only a portion of the plurality of fin-shaped channels.

17. The method of claim 15 , further comprising forming a metallic layer between the source/drain and the conductive contact, wherein the metallic layer has a third length in the longitudinal direction of the source/drain that is greater than the first length of the conductive contact.

18. The method of claim 15 , further comprising forming a metallic layer between the source/drain and the conductive contact, wherein forming the metallic layer and the conductive contact comprises:
forming a first insulation layer on the gate structure and the source/drain;
forming an opening extending through the first insulation layer and exposing the source/drain;
forming the metallic layer on the source/drain;
forming a second insulation layer on the metallic layer in the opening;
forming a contact opening extending through the second insulation layer and exposing the metallic layer; and
forming the conductive contact in the contact opening, the conductive contact contacting the metallic layer.

19. The method of claim 18 , wherein forming the gate structure comprises:
forming a dummy gate structure crossing over the plurality of fin-shaped channels;
forming a third insulation layer on sides of the dummy gate structure; and
replacing the dummy gate structure with a gate insulation layer and a gate electrode, the gate electrode comprising a met

Assignees

• Kittl Jorge A
• Hegde Ganesh
• Sengupta Rwik
• Obradovic Borna J
• Rodder Mark S
• Samsung Electronics Co Ltd

Inventors

• Kittl Jorge A
• Hegde Ganesh
• Sengupta Rwik
• Obradovic Borna J
• Rodder Mark S

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/0111

  to Group IV semiconductors · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/031

  of conductive parts of the interconnections · CPC title