Compensated readout of a memristor array, a memristor array readout circuit, and method of fabrication thereof

Patent metadata

Field	Value
Publication number	US-10297318-B2
Application number	US-201615735978-A
Country	US
Kind code	B2
Filing date	Jun 15, 2016
Priority date	Jun 17, 2015
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

A method for readout of a gated memristor array, a memristor array readout circuit and method of fabrication thereof are provided. In the context of the method, the method includes selecting a row of a memristor array associated with a desired cell, measuring the value of the selected memristor row, and selecting a column of a memristor array associated with the desired cell. The selection of the column and selection of the row selects the desired cell. The method also includes measuring the value of the memristor selected row with the selected desired cell and determining the value of the desired cell based on the value of the selected memristor row and the value of the selected memristor row with the selected desired cell.

First claim

That which is claimed:

1. A method comprising:
selecting a row of a memristor array associated with a desired memory cell;
measuring a value of a leakage current associated with the selected memristor row;
selecting a column of a memristor array associated with the desired memory cell, wherein the selection of the column and the selection of the row selects the desired memory cell;
measuring a value of (1) the leakage current associated with the memristor selected row and (2) a current associated with the selected desired cell; and
determining a value of the desired memory cell based on (1) the value of the leakage current of the selected memristor row and (2) the value of the current of the selected desired memory cell,
wherein the leakage current associated with the memristor selected row and the current associated with the selected desired cell are measured with first to fourth transistors and first and second capacitors.

2. The method of claim 1 , wherein the memristor array comprises transistor gated memory cells.

3. The method of claim 1 , wherein, determining the value of the desired cell further comprises:
subtracting a current of the selected memristor row from a current of the selected memristor row with the selected desired memory cell.

4. The method of claim 1 ,
wherein measuring the value of the selected row of the memristor array further comprises charging the first capacitor,
wherein measuring the value of the selected row of the memristor array with the selected desired memory cell further comprises charging the second capacitor, and
wherein determining the value of the desired memory cell further comprises comparing the value of the first capacitor and the value of the second capacitor.

5. The method of claim 4 ,
wherein the measuring the value the row of the memristor array further comprises activating the first transistor, wherein the first transistor is configured to control a charging path of the first capacitor, and
wherein the measuring the value of the row of the memristor array with the selected desired memory cell further comprises activating the second transistor, wherein the second transistor is configured to control a charging path of the second capacitor.

6. The method of claim 1 , further comprising:
resetting a readout circuit after the determining the value of the desired memory cell.

7. A circuit comprising;
first and second transistors configured to sample a selected row of a memristor array;
a third transistor configured to activate a charging path for a first capacitor;
a fourth transistor configured to activate a charging path for a second capacitor,
wherein the first capacitor is configured to be charged by a current associated with a first sample,
wherein the second capacitor is configured to be charged by a current associated with a second sample; and
a comparator configured to compare value of the first and second samples.

8. The circuit of claim 7 further comprising:
a fifth transistor configured to discharge the first capacitor; and
a sixth transistor configured to discharge the second capacitor.

9. The circuit of claim 7 , wherein the first and second transistors are configured as a two resistor current mirror.

10. The circuit of claim 7 , wherein the memristor array comprises transistor gated memory cells.

11. The circuit of claim 7 ,
wherein the first sample is associated with a selected row of the memristor, wherein the selected row of the memristor does not comprise a selected memory cell, and
wherein the second sample is associated with a selected row of the memristor array, wherein the selected row of the memristor array comprises a selected memory cell.

12. The circuit of claim 7 , wherein the comparator comprises a hysteresis comparator or a Schmitt-trigger comparator.

13. The circuit of claim 7 , wherein an output value of the comparator correlates to the value of the selected memory cell.

14. A method of fabricating a circuit comprising:
providing first and second transistors configured to sample a selected row of a memristor array;
providing first and second capacitors;
providing a third transistor configured to activate a charging path for the first capacitor;
providing a fourth transistor configured to activate a charging path for the second capacitor,
wherein the first capacitor is configured to be charged by a current associated with a first sample,
wherein the second capacitor is configured to be charged by a current associated with a second sample; and
providing a comparator configured to compare value of the first and second samples.

15. The method of fabricating a circuit of claim 14 further comprising:
providing a fifth transistor configured to discharge the first capacitor; and
providing a sixth transistor configured to discharge the second capacitor.

16. The method of fabricating a circuit of claim 14 , wherein the first and second transistors are configured as a two resistor current mirror.

17. The method of fabricating a circuit of claim 14 , wherein the memristor array comprises transistor gate memory cells.

18. The method of fabricating a circuit of claim 14 ,
wherein the first sample is associated with a selected row of the memristor, wherein the selected row of the memristor does not comprise a selected memory cell, and
wherein the second sample is associated with a selected row of the memristor array, wherein the selected row of the memristor array comprises a selected memory cell.

19. The method of fabricating a circuit of claim 14 , wherein the comparator comprises a hysteresis comparator or a Schmitt-trigger comparator.

20. The method of fabricating a circuit of claim 14 , wherein an output value of the comparator correlates to the value of the selected memory cell.

Assignees

• Univ King Abdullah Sci & Tech

Inventors

• Zidan Mohammed Affan
• Omran Hesham
• Salem Ahmed Sultan
• Salama Khaled Nabil

Classifications

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

• G11C27/024

  using a capacitive memory element (G11C27/04 takes precedence) · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C2013/0057

  Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value · CPC title