Optimizing the layout of circuits based on multiple design constraints

Patent metadata

Field	Value
Publication number	US-10296691-B2
Application number	US-201615191651-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

Disclosed is a system, computer program product, and method for performing logic, physical synthesis, and post-route optimization. The method begins with identifying a plurality of groups of paths in a circuit by a unique criteria. The unique criteria is any one of a netlist regular expression, a cell topology regular expression, a physical structure, or a combination thereof. An optimization process is performed on the design and is repeated until the cumulative histogram corresponds to the reference histogram within a threshold. The histogram optimization on the group of paths to make the cumulative histogram correspond to the reference cumulative histogram can be adjusted to account for timing, power, yield, or a combination thereof. After a first group of paths has been optimized, the process can be repeated for other groups of paths. The histogram optimization performed on each group of paths is merged into overall histogram optimization design.

First claim

What is claimed is:

1. A method for physically fabricating an electronic circuit using histogram optimization as part of a design process, the method comprising:
a) identifying a plurality of groups of all paths in a circuit by unique criteria, the unique criteria being any of a netlist regular expression, a cell topology regular expression, a physical structure, or a combination thereof;
b) selecting at least one group subset of paths from the plurality of groups of all paths for analysis;
c) generating a cumulative histogram for the group subset of paths that have been selected, the cumulative histogram including a cumulative path count versus a slack distribution;
d) generating a similarity score by comparing the cumulative path count versus the slack distribution of the cumulative histogram to a cumulative path count versus a slack distribution of a reference cumulative histogram for the group subset of paths that have been selected;
e) adjusting a histogram optimization on the group subset of paths that have been selected to make the cumulative histogram correspond to the reference cumulative histogram maximize the similarity score;
repeating steps d and e until the cumulative histogram corresponds to the reference cumulative histogram within a threshold; and
physically fabricating, with a computer, at least one electronic circuit based on the group subset of paths that have been selected.

2. The method of claim 1 , wherein the adjusting a histogram optimization on the group subset of paths to make the cumulative histogram correspond to the reference cumulative histogram includes making the cumulative histogram better than the reference cumulative histogram in terms of at least one of timing, power, yield, or a combination thereof.

3. The method of claim 1 , further comprising:
selecting an additional group subset of paths from the plurality of the groups of all paths for analysis and performing steps c through e with the additional group subset of paths in place of the group subset of paths that have been selected; and
merging the histogram optimization performed on each group subset of paths from the plurality of the groups of all paths into overall histogram optimization design.

4. The method of claim 1 , wherein the unique criteria for the group subset of paths includes:
timing criteria with timing violations counts, endpoint reports of path delays represented as gates and wire component delays, and timing histogram analysis attributed to gates in each the group subset of paths in order to provide both a relative power contribution of each the group subset of paths and a delta in power before and after adjusting the histogram optimization.

5. The method of claim 1 , wherein the unique criteria for the group subset of paths includes:
yield criteria with a conversion of a timing histogram to a yield metric attributed to gates in each group subset of paths in order to provide both a relative power contribution of each group subset of paths and a delta in power before and after adjusting the histogram optimization.

6. The method of claim 1 , wherein the unique criteria for the group subset of paths includes:
power criteria with a summation of gate leakage and dynamic power attributed to gates in each the group subset of paths in order to provide both a relative power contribution of each the group subset of paths and a delta in power before and after adjusting the histogram optimization.

7. The method of claim 1 , wherein the unique criteria for the group subset of paths includes:
cumulative violations across all the group subset of paths in the plurality of groups of all paths.

8. The method of claim 1 , wherein the selecting at least one group subset of paths from the plurality of groups of all paths for analysis further comprises selecting the at least one group subset of paths from multiple design scenarios by ranking the multiple design scenarios based on a comparison of the cumulative histograms of the multiple design scenarios to a reference cumulative histogram.

9. A system for physically fabricating an electronic circuit using histogram optimization as part of a design, the system comprising:
a memory;
a processor communicatively coupled to the memory, where the processor is configured to perform
a) identifying a plurality of groups of all paths in a circuit by unique criteria, the unique criteria being any of a netlist regular expression, a cell topology regular expression, a physical structure, or a combination thereof;
b) selecting at least one group subset of paths from the plurality of groups of all paths for analysis;
c) generating a cumulative histogram for the group subset of paths that have been selected, the cumulative histogram including a cumulative path count versus a slack distribution;
d) generating a similarity score by comparing the cumulative path count versus the slack distribution of the cumulative histogram to a cumulative path count versus a slack distribution of a reference cumulative histogram for the group subset of paths that have been selected;
e) adjusting a histogram optimization on the group subset of paths that have been selected to make the cumulative histogram correspond to the reference cumulative histogram maximize the similarity score;
repeating steps d and e until the cumulative histogram corresponds to the reference cumulative histogram within a threshold; and
physically fabricating, with a computer, at least one electronic circuit based on the group subset of paths that have been selected.

10. The system of claim 9 , wherein the adjusting a histogram optimization on the group subset of paths to make the cumulative histogram correspond to the reference cumulative histogram includes making the cumulative histogram better than the reference cumulative histogram in terms of at least one of timing, power, yield, or a combination thereof.

11. The system of claim 9 , further comprising:
selecting an additional group subset of paths from the plurality of the groups of all paths for analysis and performing steps c through e with the additional group subset of paths in place of the group subset of paths that have been selected; and
merging the histogram optimization performed on each group subset of paths from the plurality of the group subset of paths into overall histogram optimization design.

12. The system of claim 9 , wherein the unique criteria for the group subset of paths includes:
timing criteria with timing violations counts, endpoint reports of path delays represented as gates and wire component delays, and timing histogram analysis attributed to gates in each the group subset of paths in order to provide both a relative power contribution of each the group subset of paths and a delta in power before and after adjusting the histogram optimization.

13. The system of claim 9 , wherein the unique criteria for the group subset of paths includes:
yield criteria with a conversion of a timing histogram to a yield metric attributed to gates in each group subset of paths in order to provide both a relative power contribution of each group subset of paths and a delta in power before and after adjusting the histogram optimization.

14. The system of claim 9 , wherein the unique criteria for the group subset of paths includes:
power criteria with a summation of gate leakage and dynamic power attributed to gates in each the group subset of paths in order to provide both a relative power contribution of each the group subset of paths and a delta in power before and after adjusting the histogram optimization.

15. The system of claim 9 , wherein t

Assignees

• IBM

Inventors

• Franch Robert Louis
• GRISTEDE George Diedrich
• Ziegler Matthew Mantell

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F2217/84

  Physics · mapped topic

• G06F2217/78

  Physics · mapped topic