Dynamic re-allocation of computer bus lanes

Patent metadata

Field	Value
Publication number	US-10296484-B2
Application number	US-201514956373-A
Country	US
Kind code	B2
Filing date	Dec 1, 2015
Priority date	Dec 1, 2015
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system having a processor in communication with a module is booted. Allocation of lanes among adapters in communication with connectors of the computer bus is controlled at boot-time and, in response to detection of an additional adapter received after boot-time, an additional allocation of lanes to the additional adapter is dynamically controlled. The additional allocation includes allocating unallocated lanes to the additional adapter, and re-allocating at least one lane from the initial allocation in response to the unallocated lanes being insufficient.

First claim

We claim:

1. A system comprising:
a processor in communication with memory;
a module, the module comprising a multiplexer in communication with the processor, and two or more host bridges in communication with the multiplexer;
a plurality of connectors in communication with respective host bridges, including a first connector in communication with a first host bridge and a second connector in communication with a second host bridge, wherein each host bridge is positioned as an interface between its respective connector and the multiplexer, and wherein each connector is configured to receive a respective adapter; and
the module to:
detect an additional adapter received after boot-time, and dynamically control an additional lane allocation through the multiplexer, wherein the additional allocation comprises the module to:
classify the additional adapter, including designate the additional adapter as excluded from an initial lane allocation at boot-time;
allocate at least one unallocated lane to the additional adapter; and
in response to the at least one unallocated lane being insufficient, re-allocate at least one lane from the initial lane allocation, wherein the re-allocation comprises the module to downshift at least one connector associated with the initial lane allocation.

2. The system of claim 1 , wherein the module further comprises detector circuitry in communication with each connector, wherein the detector circuitry is configured to detect the presence of each adapter.

3. The system of claim 1 , wherein the additional allocation further comprises the module to:
determine and compare two quantities related to lanes designated by the additional adapter and unallocated lanes; and
allocate a number of lanes to the additional adapter based on the comparison, including the module to perform an action selected from the group consisting of:
allocate at least a portion of the unallocated lanes, re-allocate at least one lane from the initial allocation, and a combination thereof.

4. The system of claim 3 , wherein the module re-allocates the at least one lane of the initial allocation to the additional adapter in response to a determination that there are fewer unallocated lanes than lanes designated by the additional adapter.

5. The system of claim 4 , wherein the downshift comprises a modification of lane width associated with the at least one downshifted connector.

6. The system of claim 1 , wherein the module is comprised in a PCI-Express (PCI-e) computer bus interface.

7. The system of claim 1 , wherein the additional adapter is a hot-pluggable component, and further comprising the module to detect the additional adapter during a hot-swap, wherein the additional lane allocation is performed in response to the hot-swap.

8. The system of claim 1 , further comprising an operating system in communication with the module, the operating system facilitating networked communication between the module, the host bridges, the connectors, and the adapter.

9. A method comprising:
a module detecting an additional adapter placed in communication with a connector after boot-time, the module comprising a multiplexer in communication with a processor and two or more host bridges in communication with the multiplexer, the host bridges including a first host bridge and a second host bridge, wherein the first host bridge is in communication with a first connector and the second host bridge is in communication with a second connector, wherein each host bridge is positioned as an interface between its respective connector and the multiplexer, and wherein each connector is configured to receive a respective adapter;
and
the module dynamically controlling an additional lane allocation through the multiplexer, wherein the additional allocation comprises:
classifying the additional adapter including designating the additional adapter as excluded from an initial lane allocation at boot-time;
allocating at least one unallocated lane to the additional adapter; and
in response to the at least one unallocated lane being insufficient, re-allocating at least one lane from the initial lane allocation, wherein the re-allocations comprises the module downshifting at least one connector associated with the initial lane allocation.

10. The method of claim 9 , wherein controlling the additional allocation of lanes further comprises:
determining and comparing two quantities related to lanes designated by the additional adapter and unallocated lanes; and
allocating a number of lanes to the additional adapter based on the comparison, including performing an action selected from the group consisting of: allocating at least a portion of the unallocated lanes, re-allocating at least one lane from the initial allocation, and a combination thereof.

11. The method of claim 10 , wherein the re-allocation of the at least one lane of the initial allocation to the additional adapter is performed in response to determining that there are fewer unallocated lanes than lanes designated by the additional adapter.

12. The method of claim 11 , wherein the downshift comprises modifying lane width associated with the at least one downshifted connector.

13. The method of claim 9 , wherein the module is comprised in a PCI-Express (PCI-e) computer bus interface.

14. The method of claim 9 , wherein the additional adapter is a hot-pluggable component, and further comprising the module detecting the additional adapter during a hot-swap, wherein the additional lane allocation is performed in response to the hot-swap.

15. A computer program product comprising a computer readable storage medium having program code embodied therewith, the program code executable by a processor to:
detect an additional adapter placed in communication with a connector after boot-time, wherein the detection is performed by a module comprising a multiplexer in communication with the processor and two or more host bridges in communication with the multiplexer, the host bridges including a first host bridge and a second host bridge, wherein the first host bridge is in communication with a first connector and the second host bridge is in communication with a second connector, wherein each host bridge is positioned as an interface between its respective connector and the multiplexer, and wherein each connector is configured to receive a respective adapter;
classify the additional adapter including designate the additional adapter as excluded from an initial lane allocation at boot-time; and
dynamically control an additional lane allocation, wherein the additional lane allocation is controlled by the multiplexer, and wherein the additional allocation comprises program code to:
allocate at least one unallocated lane to the additional adapter; and
in response to the at least one unallocated lane being insufficient, re-allocate at least one lane from the initial lane allocation, wherein the re-allocation comprises program code to downshift at least one connector associated with the initial lane allocation.

16. The computer program product of claim 15 , wherein the control of the additional allocation of lanes further comprises program code to:
determine and compare two quantities related to lanes designated by the additional adapter and unallocated lanes; and
allocate a number of lanes to the additional adapter based on the comparison, including program code to perform an action selected from the group consisting of: allocate at least a portion of the unallocated lanes, re-allocate at least one lane from the initial allocation, and a combination thereof.

Assignees

• IBM

Inventors

• Garibay Victor A
• Hurlimann Daniel E
• Mehta Chetan
• Pizzano Fernando
• Sand Thomas R

Classifications

• G06F13/1678

  using bus width · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title