Mems device and process for rf and low resistance applications
US-2016031702-A1 · Feb 4, 2016 · US
US10294097B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10294097-B2 |
| Application number | US-201615291599-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 12, 2016 |
| Priority date | Nov 28, 2012 |
| Publication date | May 21, 2019 |
| Grant date | May 21, 2019 |
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A micro-electro-mechanical system device is disclosed. The micro-mechanical system device comprises a first silicon substrate comprising: a handle layer comprising a first surface and a second surface, the second surface comprises a cavity; an insulating layer deposited over the second surface of the handle layer; a device layer having a third surface bonded to the insulating layer and a fourth surface; a piezoelectric layer deposited over the fourth surface of the device layer; a metal conductivity layer disposed over the piezoelectric layer; a bond layer disposed over a portion of the metal conductivity layer; and a stand-off formed on the first silicon substrate; wherein the first silicon substrate is bonded to a second silicon substrate, comprising: a metal electrode configured to form an electrical connection between the metal conductivity layer formed on the first silicon substrate and the second silicon substrate.
Opening claim text (preview).
What is claimed is: 1. A method, comprising: depositing an insulation layer over a silicon handle substrate that comprises a first surface and a second surface, wherein the second surface comprises a cavity and the insulation layer is formed on the second surface of the silicon handle substrate; bonding a first surface of a semiconductor layer to the insulation layer; depositing a piezoelectric layer directly on a second surface of the semiconductor layer; depositing a metal conductivity layer over the piezoelectric layer; partially depositing a bond layer over the metal conductivity layer; forming a stand-off on the second surface of the semiconductor layer; and establishing an electrical connection between the metal conductivity layer and a second silicon substrate. 2. The method of claim 1 , further comprising depositing a silicon layer or a silicon dioxide layer to form the stand-off. 3. The method of claim 1 , further comprising depositing a silicon dioxide layer to form a stand-off positioned on the piezoelectric layer. 4. The method of claim 1 , further comprising performing patterning and etching of the piezoelectric layer to form a sidewall. 5. The method of claim 4 , further comprising interposing a first dielectric layer between the piezoelectric layer and the metal conductive layer. 6. The method of claim 5 , further comprising disposing a second dielectric layer on the sidewall of the piezoelectric layer. 7. The method of claim 6 , further comprising exposing the semiconductor layer via a first opening in the silicon handle substrate. 8. The method of claim 7 , further comprising exposing the piezoelectric layer through the first opening and a second opening in the semiconductor layer. 9. The method of claim 1 , further comprising selectively removing a portion of the semiconductor layer. 10. The method of claim 1 , further comprising depositing an infra-red (IR) absorption layer on a selected portion of the semiconductor layer. 11. The method of claim 1 , further comprising depositing an infra-red (IR) absorption layer on a selected portion of the piezoelectric layer.
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