Methods and circuits for adaptive equalization

Patent metadata

Field	Value
Publication number	US-10291440-B2
Application number	US-201815978506-A
Country	US
Kind code	B2
Filing date	May 14, 2018
Priority date	May 21, 2004
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

First claim

What is claimed is:

1. A receiver comprising:
a sampler to issue a decision signal indicative of when an input signal exceeds a threshold voltage;
circuitry to accumulate a first count indicative of a first number of times the input signal has a characteristic and to accumulate a second count indicative of a second number of times the input signal has the characteristic while the decision signal of the sampler indicates that the input signal exceeds the threshold voltage; and
control logic to adjust a parameter of the receiver responsive to the first count and the second count.

2. The receiver of claim 1 , wherein the input signal expresses symbols and the characteristic includes a pattern of the symbols.

3. The receiver of claim 1 , the control logic to adjust the parameter of the receiver responsive to a ratio of the first count and the second count.

4. The receiver of claim 1 , wherein the input signal exhibits an eye opening over time and the control logic adjusts the parameter to increase the eye opening.

5. The receiver of claim 1 , further comprising an equalizer to receive and equalize a data signal to produce the input signal as an equalized data signal.

6. The receiver of claim 5 , further comprising a data filter to issue an enable signal responsive to a pattern in the input signal.

7. The receiver of claim 6 , wherein the pattern includes at least one transition of the input signal.

8. The receiver of claim 5 , wherein the control logic, to adjust the parameter, adjusts an equalization setting of the equalizer.

9. The receiver of claim 1 , wherein the sampler issues the decision signal in synchronization with a sample-clock signal.

10. The receiver of claim 9 , further comprising a second sampler to issue a second detection signal in synchronization with a data-clock signal.

11. The receiver of claim 10 , wherein the sample-clock signal is of a lower frequency than the data-clock signal.

12. A method of equalizing an input signal to produce an equalized signal of an equalized-signal amplitude, the method comprising:
equalizing the input signal at an equalizer setting;
accumulating a first count indicative of a first number of times the equalized signal exhibits a characteristic;
accumulating a second count indicative of a second number of times the equalized signal exceeds a threshold while exhibiting the characteristic; and
adjusting the equalizer setting responsive to the first count and the second count.

13. The method of claim 12 , wherein the equalized signal expresses symbols and the characteristic includes a pattern of the symbols.

14. The method of claim 13 , wherein the pattern of the symbols includes at least one transition of the equalized signal.

15. The method of claim 12 , wherein adjusting the equalizer setting responsive to the first count and the second count comprises adjusting the equalizer responsive to a ratio of the first count to the second count.

16. The method of claim 12 , wherein the equalized signal exhibits an eye opening over time, and wherein the second count is a function of the eye opening.

17. The method of claim 12 , further comprising adjusting the threshold responsive to at least one of the first count and the second count.

18. The method of claim 17 , wherein the threshold comprises a voltage.

19. The method of claim 12 , further comprising sampling the equalized signal in synchronization with a sample-clock signal of a first frequency and accumulating the first count in synchronization with a second clock signal of a second frequency lower than the first frequency.

20. The method of claim 19 , further comprising accumulating the second count in synchronization with the second clock signal.

Assignees

• Rambus Inc

Inventors

• Farjad-Rad Ramin

Classifications

• H04B3/145

  variable equalisers · CPC title

• H04B10/40

  Transceivers · CPC title

• H04L2025/03681

  Control of adaptation · CPC title

• H04L25/03885

  adaptive · CPC title

• H04L25/03159 Primary

  operating in the frequency domain (H04L25/03165, H04L25/03178 take precedence) · CPC title