Transceiver and method for reducing a self-interference of a transceiver

Patent metadata

Field	Value
Publication number	US-10291384-B2
Application number	US-201815868728-A
Country	US
Kind code	B2
Filing date	Jan 11, 2018
Priority date	Jul 15, 2015
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A transceiver includes an antenna arrangement configured for interfacing a wireless transmission channel and including an interface for receiving a sending signal and an interface for providing a receiving signal. The transceiver includes a main transmitter, an analog domain filter, an auxiliary transmitter, a radio frequency interference removal stage, a main receiver, a feedback receiver and a processor configured performing digital signal operations. The transceiver is configured for performing interference cancellation on a receiving signal in a radio frequency domain and in a digital domain.

First claim

The invention claimed is:

1. A transceiver comprising:
an antenna arrangement configured for interfacing a wireless transmission channel and comprising an interface for receiving a sending signal and an interface for providing a receiving signal;
a main transmitter connected to the antenna arrangement and configured for generating the sending signal based on a digital transmission signal;
an analog domain filter configured for generating a first interference cancellation signal from the sending signal;
an auxiliary transmitter configured for generating a second interference cancellation signal based on a digital auxiliary signal;
a radio frequency interference removal stage for performing interference cancellation on the receiving signal using the first interference cancellation signal and the second interference cancellation signal to acquire a preliminary enhanced signal;
a main receiver configured for receiving the preliminary enhanced signal and for providing a digital receiving signal;
a feedback receiver configured for providing a feedback signal based on the preliminary enhanced signal at a first operating mode and based on the sending signal at a second operating mode; and
a processor configured for receiving the digital receiving signal, for receiving the feedback signal, for providing the digital transmission signal based on an input information signal and for providing the digital auxiliary signal based on the input information signal;
wherein the processor comprises a linear pre-equalizer configured for pre-equalizing the digital auxiliary signal based on the digital receiving signal;
wherein the processor comprises a digital self-interference canceller configured for determining a digital interference cancellation signal based on the input signal and based on the digital receiving signal;
wherein the processor comprises a digital interference removal stage configured for performing digital interference cancellation on the digital receiving signal using the digital interference cancellation signal to acquire an enhanced receiving signal; and
wherein the processor is configured for parametrizing the analog domain filter based on an evaluation of the feedback signal received from the feedback receiver in the first operating mode and in the second operating mode and for parametrizing the linear pre-equalizer based on the digital receiving signal.

2. The transceiver according to claim 1 , wherein the feedback receiver comprises a multiplexer configured for receiving the preliminary enhanced signal and the sending signal and for providing the preliminary enhanced signal at an output of the multiplexer when being in the first operating mode and for providing the sending signal at the output when being in the second operating mode.

3. The transceiver according to claim 1 , wherein the processor is configured for determining a measure relating to the digital interference cancellation signal being deterministic, to control the digital self-interference canceller so as to determine the digital interference cancellation signal based on the input signal and based on the digital receiving signal when the measure is above a threshold value or equal to the threshold value, and to control the digital self-interference canceller so as to determine the digital interference cancellation signal based on the feedback signal and based on the digital receiving signal when the measure is below a threshold value.

4. The transceiver according claim 3 , wherein the processor is configured for determining the measure relating to the digital interference cancellation signal being deterministic based on a correlation of the input signal and the digital receiving signal.

5. The transceiver according to claim 1 ,
wherein, during a first time interval, the processor is configured to provide the digital transmission signal to the main transmitter and to control the feedback receiver such that the feedback receiver operates in the first operating mode, wherein the processor is configured for determining a parameter of the linear pre-equalizer and for parametrizing the analog domain filter based on the feedback signal; and
wherein, during a second time interval, the processor is configured to provide the digital auxiliary signal to the auxiliary transmitter and to control the feedback receiver such that the feedback receiver operates in the second operating mode, wherein the processor comprises a further linear pre-equalizer configured for pre-equalizing the digital transmission signal based on the digital feedback signal.

6. The transceiver according to claim 1 , wherein the processor is configured for parametrizing the analog domain filter based on the feedback signal.

7. The transceiver according to claim 1 , wherein the feedback receiver is configured for providing the feedback signal based on the second interference cancellation signal at a third operating mode; wherein the processor is configured for pre-equalizing the digital transmission signal based on the feedback signal.

8. The transceiver according to claim 1 , wherein the feedback receiver comprises a radio frequency multiplexer configured for receiving the preliminary enhanced signal and the sending signal and to provide the preliminary enhanced signal while not providing the sending signal during the first operating mode of the feedback receiver and for providing the sending signal while not providing the preliminary enhanced signal during the second operating mode of the feedback receiver.

9. The transceiver according to claim 1 , wherein the processor comprises a further linear pre-equalizer configured for pre-equalizing the digital auxiliary signal based on the digital receiving signal or based on the feedback signal.

10. The transceiver according to claim 1 , wherein the processor is configured for using the feedback receiver for determining a parameter of the analog domain filter and for deactivating the feedback receiver during an active transmission phase between the transceiver and a further transceiver.

11. The transceiver according to claim 1 , wherein the analog domain filter is configured for generating the first interference cancellation signal based on a signal inversion, based on an attenuation and based on a phase manipulation, wherein the processor is configured for adapting a parameter of the attenuation or of the phase manipulation.

12. The transceiver according to claim 11 , wherein the analog domain filter comprises an attenuation network configured for attenuating a received signal and a delay network configured for delaying a received signal for acquiring the phase manipulation or a phase shifter for phase shifting a received signal for acquiring the phase manipulation.

13. The transceiver according to claim 1 , wherein the processor is configured for adjusting a down-conversion frequency of the main receiver or of the feedback receiver or for adjusting an up-conversion frequency of the main transmitter or of the auxiliary transmitter so as to adjust a frequency band of the transceiver used for transmitting and/or sending.

14. The transceiver according to claim 1 , wherein the antenna arrangement comprises an antenna element for transmitting the sending signal to the wireless transmission channel and for receiving the receiving signal from the wireless transmission channel or wherein the antenna arrangement comprises a first antenna element configured for transmitting the sending signal to the wireless transmission channel and comprises a second antenna element configured for receiving the receiving signal from the wireless transmission channel.

15. The

Assignees

• Fraunhofer Ges Forschung

Inventors

• Askar Ramez
• Schubert Benjamin
• Keusgen Wilhelm

Classifications

• H04B1/123 Primary

  using adaptive balancing or compensation means (adaptive filter circuits and algorithms H03H) · CPC title

• H04B1/44

  Transmit/receive switching · CPC title

• H04L5/1461 Primary

  Suppression of signals in the return path, i.e. bidirectional control circuits · CPC title

• H04B1/1027 Primary

  assessing signal quality or detecting noise/interference for the received signal · CPC title

• H04B2001/3855

  carried in a belt or harness · CPC title