Digital signal processing of an optical communications signal in a coherent optical receiver

Patent metadata

Field	Value
Publication number	US-10291331-B2
Application number	US-201515525670-A
Country	US
Kind code	B2
Filing date	Feb 9, 2015
Priority date	Nov 13, 2014
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A digital signal processing, DSP, unit ( 10 ) for use in a coherent optical receiver for an optical communications network. The DSP unit comprises an adaptive equalizer ( 12 ) and a processing block ( 22 ). The equalizer ( 12 ) comprises input ports for receiving electrical signals, each corresponding to a different state of polarization of an optical signal received by the coherent optical receiver, and output ports, each connected to a processing branch ( 14 ). A processing branch comprises a symbol sequence estimator, SSE, ( 16 ) and a carrier phase estimator, CPE, ( 18 ) comprising an input for receiving signal taped from an output of the processing branch. An output of the CPE is connected to a phase adjuster ( 20 ) interconnecting the respective output port of the equalizer and the SSE. The processing block ( 22 ) is connected to an output of the CPE, an output of the processing branch and at least one of the output of the phase adjuster and the outputs of the equalizer.

First claim

The invention claimed is:

1. A digital signal processing unit for use in a coherent optical receiver for an optical communications network, the digital signal processing unit comprising:
an adaptive equalizer comprising:
a number of input ports for receiving electrical signals, each electrical signal corresponding to a different state of polarization of an optical signal received by the coherent optical receiver; and
a number of output ports,

wherein each of the output ports is connected to a processing branch, and
wherein the processing branch comprises:
at least one symbol sequence estimator; and
a carrier phase estimator comprising an input for receiving a signal tapped from an output of the processing branch,
wherein an output of the carrier phase estimator is connected to a phase adjuster interconnecting the respective output port of the adaptive equalizer and the at least one symbol sequence estimator; and

a processing block connected to the output of the carrier phase estimator, the output of the processing branch, at least one output of the phase adjuster, and outputs of the adaptive equalizer.

2. The digital signal processing unit of claim 1 , wherein the processing block is configured to:
perform simultaneous channel response coefficients estimation and equalizer coefficients estimation;
provide resulting channel response coefficients to the at least one symbol sequence estimator; and
provide resulting equalizer coefficients to the adaptive equalizer.

3. The digital signal processing unit of claim 2 , wherein:
the processing block is further configured to perform a gradient algorithm consisting of a first relationship for estimating the equalizer coefficients and a second relationship for estimating the channel response coefficients; and
the at least one symbol sequence estimator is configured to perform a symbol sequence estimation algorithm using the channel response coefficients.

4. The digital signal processing unit of claim 3 , wherein the gradient algorithm is an iterative data-aided stochastic-gradient algorithm arranged to minimize an error (e k ) between a selected equalized signal sample output from the adaptive equalizer and an estimated channel symbol.

5. The digital signal processing unit of claim 4 ,
wherein the first relationship is arranged to estimate an equalizer coefficient C (k+1) by subtracting a first update value from a preceding equalizer coefficient C (k) , the first update value being proportional to the error e k , and
wherein the second relationship is arranged to estimate a channel response coefficient h (k+1) by adding a second update value to a preceding channel response coefficient h (k) , the second update value being proportional to the error e k .

6. The digital signal processing unit of claim 1 ,
wherein the first relationship is:
C i (k+1) =C i (k) −a c ( g k ∘e k ) s k−i † ,0≤ i≤N c −1,

where a c is a first step-size gain, g k is a column vector of phase estimates for a k-th equalized signal sample (sk), and N c is a number of taps of the adaptive equalizer; and
wherein the second relationship is:
h i (k+1) =h i (k) +a h ( e k ∘x k−i *+e k *∘x k+i ),1≤ i≤L T ,

where a h is a second step-size gain, x k+1 is a column vector of transmitted symbols, and L T is a number of signal samples used by the at least one symbol sequence estimator.

7. The digital signal processing unit of claim 1 , wherein each of the output ports of the adaptive equalizer is connected to a separate processing branch wherein each separate processing branch comprises:
the at least one symbol sequence estimator;
the carrier phase estimator; and
the phase adjuster interconnecting respective output port of the adaptive equalizer and the at least one symbol sequence estimator, and

wherein the processing block is connected to an output of each carrier phase estimator, outputs of processing branches, at least one output of outputs of the phase adjuster, and outputs of the adaptive equalizer.

8. The digital signal processing unit of claim 7 ,
wherein each separate processing branch comprises two symbol sequence estimators arranged in parallel, wherein one of the two symbol sequence estimators receives an in-phase component and the other of the two symbol sequence estimators receives a quadrature component of a signal output from the adaptive equalizer; and
wherein the output of the carrier phase estimator of each branch is connected to the phase adjuster interconnecting the respective output port of the adaptive equalizer and the two symbol sequence estimators.

9. The digital signal processing unit of claim 7 ,
wherein each separate processing branch further comprises a respective forward error correcting (FEC) decoder connected to an output of each symbol sequence estimator of the two symbol sequence estimators, and
wherein inputs of the carrier phase estimator are tapped from an output of the respective FEC decoder.

10. The digital signal processing unit of claim 1 , wherein the at least one symbol sequence estimator is one of a maximum a posteriori (MAP) detector and a maximum likelihood sequence detector.

11. The digital signal processing unit of claim 10 , wherein the MAP detector is a Bahl, Cocke, Jelinek, Raviv (BCJR) detector.

12. The digital signal processing unit of claim 1 ,
wherein the carrier phase estimator is a decision directed carrier phase estimation unit, and
wherein the phase adjuster is a complex multiplier.

13. A coherent optical receiver for use in an optical communications network, the coherent optical receiver comprising:
an optical input arranged to receive an optical signal;
a splitter arranged to split the received optical signal into two orthogonal states of polarization;
a laser arranged to operate as a local oscillator to generate a second optical signal;
two 2×2 90° optical hybrids arranged to combine optical fields of the two orthogonal states of polarization received from the splitter with optical field of the second optical signal; and
four pairs of balanced photodetectors, a first two pairs of the balanced photodetectors connected to a first optical hybrid and a second two pairs of the balanced photodetectors connected to a second optical hybrid,
the four pairs of balanced photodetectors comprising four outputs arranged to output electrical signals representing in-phase and quadrature components of the two orthogonal states of polarization of the received optical signal, wherein the four outputs are connected to four analog-to-digital converters and outputs of the four analog-to-digital converters are connected to a digital signal processing unit,
wherein the digital signal processing unit comprising:
A an adaptive equalizer comprising:
a number of input ports for receiving the electrical signals, each electrical signal corresponding to a different state of polarization of the optical signal received by the coherent optical receiver; and
a number of output ports,

wherein each of the output ports is connected to a processing branch, and wherein the processing branch comprises:
at least one symbol sequence estimator; and
a carrier phase estimator comprising an input for receiving a signal tapped from an output of the processing branch,
wherein an output of the carrier phase estimator is connected to a phase adjuster interconnecting respective output port of the adaptive equalizer and the at least one symbol sequence estimator; and

a processing block connected to the output of the carrier phase estimator, the output of the processing branch, at least one output of the

Assignees

• Ericsson Telefon Ab L M

Inventors

• Cavaliere Fabio
• Secondini Marco

Classifications

• H04B10/6165

  Estimation of the phase of the received optical signal, phase error estimation or phase error correction · CPC title

• H04B10/64

  Heterodyne {, i.e. coherent receivers where, after the opto-electronic conversion, an electrical signal at an intermediate frequency [IF] is obtained} · CPC title

• H04J14/02

  Wavelength-division multiplex systems · CPC title

• H04L25/03178 Primary

  Arrangements involving sequence estimation techniques · CPC title

• H04B10/616 Primary

  Details of the electronic signal processing in coherent optical receivers · CPC title