System and method for biasing an RF circuit

Patent metadata

Field	Value
Publication number	US-10291194-B2
Application number	US-201715728264-A
Country	US
Kind code	B2
Filing date	Oct 9, 2017
Priority date	Oct 9, 2017
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

In accordance with an embodiment, a circuit includes: a replica input transistor, a first replica cascode transistor, an active current source, and an active cascode biasing circuit. The active current source is configured to set a current flowing through the first replica cascode transistor and the replica input transistor to a predetermined value by adjusting a voltage of a control node of the replica input transistor; and an active cascode biasing circuit including a first output coupled to the control node of the first replica cascode transistor, and the active cascode biasing circuit configured to set a drain voltage of the replica input transistor to a predetermined voltage by adjusting a voltage of the control node of the first replica cascode transistor.

First claim

What is claimed is:

1. A circuit comprising:
a replica input transistor comprising a first control node configured to be coupled to a second control node of an input transistor of an RF circuit;
a first replica cascode transistor coupled in series with the replica input transistor, the first replica cascode transistor comprising a third control node configured to be coupled to a fourth control node of a first cascode transistor of the RF circuit;
an active current source circuit having a first output coupled to the first control node of the replica input transistor, the active current source circuit configured to set a current flowing through the first replica cascode transistor and the replica input transistor to a predetermined value by adjusting a voltage of the first control node of the replica input transistor; and
an active cascode biasing circuit comprising a first output coupled to the third control node of the first replica cascode transistor, the active cascode biasing circuit configured to set a drain voltage of the replica input transistor to a predetermined voltage by adjusting a voltage of the third control node of the first replica cascode transistor, wherein the active cascode biasing circuit comprises a second amplifier having a first input coupled to a drain of the replica input transistor, a second input coupled to a bias reference voltage node, and an output coupled to the third control node of the first replica cascode transistor.

2. The circuit of claim 1 , further including the RF circuit comprising the input transistor and the first cascode transistor.

3. The circuit of claim 2 , wherein the RF circuit is a low noise amplifier circuit.

4. The circuit of claim 1 , further comprising a second replica cascode transistor coupled in series with the first replica cascode transistor, the second replica cascode transistor comprising a fifth control node configured to be coupled to a sixth control node of a second cascode transistor of the RF circuit, wherein the active cascode biasing circuit further comprises a second output coupled to the fifth control node of the second replica cascode transistor.

5. The circuit of claim 4 , wherein the active cascode biasing circuit comprises a level shifting circuit coupled between the first output and the second output of the active cascode biasing circuit.

6. The circuit of claim 1 , wherein the active current source circuit comprises:
a reference current source;
a first resistor coupled between a reference voltage node and the reference current source at a first node;
a second resistor coupled between a drain of the first cascode transistor and the reference voltage node; and
a first amplifier having a first input coupled to the first node, a second input coupled to the drain of the first cascode transistor and an output coupled to the first control node of the replica input transistor.

7. The circuit of claim 1 , further comprising a digital-to-analog converter having an output coupled to the bias reference voltage node.

8. A method of biasing an RF circuit comprising an input transistor coupled in series with a first cascode transistor using a biasing circuit comprising a replica input transistor coupled in series with a first replica cascode transistor, the method comprising:
setting a current flowing through the first replica cascode transistor and the replica input transistor to a predetermined value by adjusting a voltage of a first control node of the replica input transistor;
setting a drain voltage of the replica input transistor to a predetermined voltage by adjusting a voltage of a second control node of the first replica cascode transistor;
applying a voltage at the second control node of the first replica cascode transistor to a third control node of the first cascode transistor of the RF circuit; and
applying a voltage at the first control node of the replica input transistor to a third control node of the input transistor of the RF circuit, wherein setting the drain voltage of the replica input transistor to the predetermined voltage comprises
measuring a voltage difference between a voltage at a bias reference voltage node and the drain voltage of the replica input transistor,
amplifying the measured voltage difference using an amplifier, and
applying the amplified measured voltage difference to the second control node of the first replica cascode transistor.

9. The method of claim 8 , wherein setting the current flowing through the first replica cascode transistor and the replica input transistor comprises:
measuring a voltage difference between a first voltage across a first resistor coupled between a reference current source and a reference voltage node, and a second voltage across a second resistor coupled between a drain of the first replica cascode transistor and the reference voltage node;
amplifying the measured voltage difference using an amplifier; and
applying the amplified measured voltage difference to the first control node of the replica input transistor.

10. The method of claim 9 , further comprising:
lowpass filtering a power supply voltage; and
applying the lowpass filtered power supply voltage to the reference voltage node.

11. The method of claim 8 , further comprising generating a voltage at the bias reference voltage node using a digital-to-analog converter.

12. The method of claim 8 , wherein:
the RF circuit further comprises a second cascode transistor coupled in series with the first cascode transistor, and the biasing circuit further comprises a second replica cascode transistor coupled in series with the replica input transistor; and
the method further comprises level shifting the voltage of the second control node of the first replica cascode transistor, and applying the level shifted voltage to a fourth control node of the second replica cascode transistor and to a fifth control node of the second cascode transistor.

13. A circuit comprising:
an RF circuit comprising
a first cascode transistor,
an input transistor coupled in series with the first cascode transistor,
an inductive degeneration circuit coupled between a first load path of the input transistor and a ground node, and
an inductive pullup circuit coupled between a second load path of the first cascode transistor and a power supply node; and

a bias circuit comprising
a first replica cascode transistor having a first control node coupled to a second control node of the first cascode transistor,
a replica input transistor coupled in series with the first replica cascode transistor, wherein a third control node of the replica input transistor is coupled to a fourth control node of the input transistor of the RF circuit,
a replica degeneration circuit coupled between a third load path of the replica input transistor and the ground node,
a first resistor having a first terminal coupled to the power supply node and a second terminal coupled to a reference current node,
a second resistor having a first terminal coupled to the power supply node and a second terminal coupled to the first replica cascode transistor,
a first amplifier having a first input coupled to the reference current node, a second input coupled to the second terminal of the second resistor, and an output coupled to a fifth control node of the first replica input transistor, and
a second amplifier having a first input coupled to a bias reference voltage node, a second input coupled to a load path terminal of the replica input transistor that is coupled to the first replica cascode transistor and an output coupled to the first control node of the first replica cascode transistor.

Assignees

• Infineon Technologies Ag

Inventors

• Ilkov Nikolay
• Baenisch Andreas
• Pfann Peter
• Wohlmuth Hans-Dieter

Classifications

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F2200/18

  the bias of the gate of a FET being controlled by a control signal · CPC title

• H03F1/0205

  in transistor amplifiers · CPC title

• H03F2200/534

  Transformer coupled at the input of an amplifier · CPC title

• H03F2200/555

  A voltage generating circuit being realised for biasing different circuit elements · CPC title