Nanowire formation methods

Patent metadata

Field	Value
Publication number	US-10290768-B2
Application number	US-201715704982-A
Country	US
Kind code	B2
Filing date	Sep 14, 2017
Priority date	Sep 14, 2017
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

Methods of forming an integrated InGaN/GaN or AlInGaP/InGaP LED on Si CMOS for RGB colors and the resulting devices are provided. Embodiments include forming trenches having a v-shaped bottom through an oxide layer and a portion of a substrate; forming AlN or GaAs in the v-shaped bottom; forming a n-GaN or n-InGaP pillar on the AlN or GaAs through and above the first oxide layer; forming an InGaN/GaN MQW or AlInGaP/InGaP MQW over the n-GaN or n-InGaP pillar; forming a p-GaN or p-InGaP layer over the n-GaN pillar and InGaN/GaN MQW or the n-InGaP pillar and AlInGaP/InGaP MQW down to the first oxide layer; forming a TCO layer over the first oxide layer and the p-GaN or p-InGaP layer; forming a second oxide layer over the TCO layer; and forming a metal pad on the TCO layer above each n-GaN or n-InGaP pillar.

First claim

What is claimed is:

1. A method comprising:
forming a plurality of trenches through a first oxide layer and a portion of a silicon (Si) substrate, each trench having a v-shaped bottom;
forming aluminum nitride (AlN) or gallium arsenide (GaAs) in the v-shaped bottom;
forming a n-type gallium nitride (n-GaN) or indium gallium phosphide (n-InGaP) pillar on the AlN or GaAs, respectively, through and above the first oxide layer;
forming an indium gallium nitride (InGaN) and gallium nitride (GaN) or aluminum indium gallium phosphide (AlInGaP) and InGaP multiple quantum well (MQW) (InGaN/GaN MQW or AlInGaP/InGaP MQW) over the n-GaN or n-InGaP pillar, respectively;
forming a p-type gallium nitride (p-GaN) or indium gallium phosphide (p-InGaP) layer over the n-GaN pillar and InGaN/GaN MQW or the n-InGaP pillar and AlInGaP/InGaP MQW, respectively, down to the first oxide layer;
forming a transparent conductive oxide (TCO) layer over the first oxide layer and the p-GaN or p-InGaP layer;
forming a second oxide layer over the TCO layer; and
forming a metal pad on the TCO layer above each n-GaN or n-InGaP pillar.

2. The method of claim 1 , comprising forming each trench by:
forming a nitride layer over the Si substrate;
patterning the nitride layer and the Si substrate to form plurality of Si fins or nanowires over the Si substrate;
forming the first oxide layer over the Si substrate;
planarizing the first oxide layer down to the nitride layer; and
etching the nitride layer, plurality of Si fins or nanowires, and a portion of the Si substrate with tetramethylammonium hydroxide (TMAH), forming the plurality of trenches.

3. The method according to claim 2 , comprising forming each Si fin or nanowire with a width or diameter of 50 nanometer (nm) to 600 nm.

4. The method according to claim 2 , comprising etching the portion of the Si substrate to a depth of 150 nm to 300 nm.

5. The method according to claim 1 , comprising forming the AlN or GaAs, each n-GaN or n-InGaP pillar, InGaN/GaN or AlInGaP/InGaP MQW, and p-GaN or p-InGaP, respectively, by metalorganic chemical vapor deposition (MOCVD).

6. The method according to claim 1 , further comprising forming an InGaN/GaN MQW or an AlInGaP/InGaP MQW over the n-GaN or n-InGaP pillar prior to forming the p-GaN or p-InGaP layer, respectively.

7. The method according to claim 1 , further comprising:
removing the Si substrate, the AlN or GaAs, and a portion of the first oxide layer and n-GaN or n-InGaP pillars, respectively;
forming a second TCO layer over a remaining portion of the first oxide layer and n-GaN or n-InGaP pillars; and
connecting each metal pad to a Si complementary metal-oxide-semiconductor (CMOS) wafer.

8. The method according to claim 7 , wherein the remaining portion comprises at least a thickness of 0.5 micrometer (μm) to 1 μm.

Assignees

• Globalfoundries Inc

Inventors

• Banna Srinivasa
• Nayak Deepak

Classifications

• H10W90/00

  Package configurations · CPC title

• H01L27/15

  Electricity · mapped topic

• H01L33/42

  Electricity · mapped topic

• H01L33/0079

  Electricity · mapped topic

• H01L33/62

  Electricity · mapped topic