Front-illuminated photosensitive logic cell

Patent metadata

Field	Value
Publication number	US-10290667-B2
Application number	US-201615335123-A
Country	US
Kind code	B2
Filing date	Oct 26, 2016
Priority date	Oct 28, 2015
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

Photosensitive logic cell on a semiconductor-on-insulator substrate, possessing a P type transistor and an N type transistor fabricated on the front face of the substrate and whose respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors, the photosensitive zone possessing a photo-detection region whose arrangement is such that it favours illumination by the face of the photosensitive zone.

First claim

The invention claimed is:

1. A device comprising at least one photosensitive logic cell, the cell comprising:
a first P type transistor and a second N type transistor, the first and second transistors resting on a semiconductor-on-insulator substrate, with the substrate comprising a surface semiconductor layer comprising a channel zone of the first transistor and a channel zone of said second transistor, with an insulating layer separating the surface semiconductor layer from a semiconductor support layer, the support layer comprising at least one photosensitive zone configured to convert photons into charge carriers, with the insulating layer being configured so as to allow electrostatic coupling between the photosensitive zone and the surface semiconductor layer, in such a way that the first transistor and the second transistor have a first threshold voltage and a second threshold voltage respectively that are modulated according to a quantity of photons received by the photosensitive zone, with the photosensitive zone being formed of a N doped zone and a superimposed P doped zone forming a first junction arranged opposite the channel zone of said first transistor and a second junction opposite the channel zone of said second transistor, with the photosensitive zone furthermore comprising a photo-detection region through which a luminous flux enters,
the surface semiconductor layer of the substrate comprising an opening such that the surface semiconductor layer does not extend opposite the photo-detection region.

2. The device according to claim 1 wherein the first transistor and the second transistor respectively comprise a first gate and a second gate arranged on the surface semiconductor layer, the cell comprising an additional gate electrode arranged at a periphery of the cell around a region of the cell where the first gate and the second gate are arranged.

3. The device according to claim 2 , wherein the additional gate electrode forms a closed outline around the first gate and the second gate.

4. The device according to claim 2 , comprising another cell juxtaposed with said cell, where the surface semiconductor layer is continuous between the cell and the another cell, with no insulating zone between said cell and said other cell within the surface semiconductor layer.

5. The device according to claim 2 , wherein the first gate and the second gate are arranged opposite another region of the photosensitive zone located at a periphery of the photo-detection region.

6. The device according to claim 1 , wherein the insulating layer of the substrate extends opposite the photo-detection region.

7. The device according to claim 1 , the cell furthermore comprising a charge evacuation transistor connected to the photosensitive zone.

8. The device according to claim 7 , the charge evacuation transistor and the photosensitive zone being connected by at least one connection element in contact with the photo-detection region and which passes into said opening.

9. The device according to claim 7 , further comprising a biasing control circuit configured to apply a signal to the charge evacuation transistor, the signal having a variable state and applied in such a way as to block the charge evacuation transistor when a reading of a logic state at output of the cell is carried out, and in such a way as to render the charge evacuation transistor pass-through when an erasure of the logic state at the output of the cell is performed.

10. The device according to claim 1 , wherein the first transistor and the second transistor are of Fully Depleted Silicon on Insulator (FDSOI) type.

Assignees

• Commissariat Energie Atomique

Inventors

• Rozeau Olivier
• Grenouillet Laurent

Classifications

• H01L27/1446 Primary

  Electricity · mapped topic

• G02F3/022

  based on electro-, magneto- or acousto-optical elements (G02F3/028 takes precedence) · CPC title

• H10F39/107 Primary

  having multiple elements covered by H10F30/00 in a repetitive configuration, e.g. radiation detectors comprising photodiode arrays · CPC title