ESD protection device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10290624-B2
Application number	US-201715730419-A
Country	US
Kind code	B2
Filing date	Oct 11, 2017
Priority date	Oct 12, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

Disclosed is an ESD protection device, comprising: a semiconductor substrate; a semiconductor buried layer located in the semiconductor substrate; an epitaxial semiconductor layer located on the semiconductor substrate and comprising a first doped region and a second doped region, wherein the semiconductor substrate and the first doped region are of a first doping type, the semiconductor buried layer, the epitaxial semiconductor layer and the second doped region are of a second doping type, the first doping type and the second doping type are opposite to each other, and the first doped region forms a plurality of interfaces with the epitaxial semiconductor layer. The disclosure improves protection performance and maximum current bearing capacity without increasing parasitic capacitance of the ESD protection device.

First claim

The invention claimed is:

1. An ESD protection device, comprising:
a semiconductor substrate;
a semiconductor buried layer located in said semiconductor substrate;
an epitaxial semiconductor layer located on said semiconductor substrate and comprising a first doped region and a second doped region,
wherein said semiconductor substrate and said first doped region are of a first doping type, said semiconductor buried layer, said epitaxial semiconductor layer and said second doped region are of a second doping type, said first doping type and said second doping type are opposite to each other, and said first doped region forms a plurality of interfaces with said epitaxial semiconductor layer,
wherein said ESD protection device further comprises a third doped region which penetrates through said epitaxial semiconductor layer to said semiconductor buried layer and said third doped region is of said second doping type,
wherein said first doped region and said second doped region are connected to each other to a first terminal, and said third doped region is connected to a second terminal.

2. The ESD protection device according to claim 1 , wherein said first doped region comprises a plurality of sub-regions which are respectively formed in said epitaxial semiconductor layer, and said plurality of sub-regions form said respective plurality of interfaces with said epitaxial semiconductor layer, respectively.

3. The ESD protection device according to claim 2 , wherein said plurality of sub-regions are circular, square, or rectangular.

4. The ESD protection device according to claim 1 , wherein said first doped region is an annular region being formed in said epitaxial semiconductor layer, and said annular region comprises an inner surface and an outer surface, said inner surface and said outer surface form said plurality of interfaces with said epitaxial semiconductor layer, respectively.

5. The ESD protection device according to claim 4 , wherein said annular region is circular, square, or rectangular.

6. The ESD protection device according to claim 1 , further comprising: an isolation layer being formed between said first doped region and said second doped region in said epitaxial semiconductor layer.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Yao Fei
• Wang Shijun
• Yin Dengping

Classifications

• H01L29/861

  Electricity · mapped topic

• H01L27/0248 Primary

  Electricity · mapped topic

• H01L29/0692

  Electricity · mapped topic

• H01L27/0255

  Electricity · mapped topic

• H01L29/66007

  Electricity · mapped topic