Semiconductor packages and methods of forming same

Patent metadata

Field	Value
Publication number	US-10290611-B2
Application number	US-201815980541-A
Country	US
Kind code	B2
Filing date	May 15, 2018
Priority date	Jul 27, 2017
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.

First claim

What is claimed is:

1. A package comprising:
a first package structure comprising:
a first die having a first active side and a first back-side, the first active side comprising a first bond pad and a first insulating layer;
a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side comprising a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds; and
a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads, wherein there is a void surrounding the conductive bonding material and between the first and second bond pad, a height of the void being less than a combined height of the first insulating layer and the second insulating layer.

2. The package of claim 1 , wherein the first insulating layer is bonded to the second insulating layer with respective bonds comprising O—H bonds.

3. The package of claim 1 , wherein the first bond pad is recessed into the first insulating layer.

4. The package of claim 1 , wherein the first insulating layer and the second insulating layer are both made of a polymer.

5. The package of claim 1 , wherein the first insulating layer and the second insulating layer are both made of silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or a combination thereof.

6. The package of claim 1 , wherein the first package structure further comprises:
a conductive pad on the first active side of the first die;
a first through via electrically coupled to the conductive pad;
a first encapsulant on the first die and laterally encapsulating the second die and the first through via, the first through via extending through the first encapsulant; and
a first redistribution structure over the second die, the first through via, and the first encapsulant, the first redistribution structure being electrically coupled to the first through via.

7. The package of claim 6 , wherein the first package structure further comprises:
a second through via adjacent the first die; and
a second encapsulant encapsulating the first die, the first encapsulant, and the second through via, the second through via extending through the second encapsulant, the first redistribution structure being electrically coupled to the second through via.

8. The package of claim 7 further comprising:
a second package structure bonded to the second through via by a first conductive connector.

9. The package of claim 1 , wherein the conductive bonding material is a solder material, and wherein the first and second bonding pads comprise copper or aluminum.

10. A method comprising:
forming a first package comprising:
bonding a first side of a first die to a second side of a second die with a conductive bonding material and a first and second insulating layers, the first side comprising a first bond pad and the first insulating layer, the second side comprising a second bond pad and the second insulating layer, the second side of the second die facing the first side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, the conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads, wherein after the bonding, a void remains around the conductive bonding material, a sidewall and a topmost surface of the first bond pad being exposed to the void.

11. The method of claim 10 , wherein forming the first package further comprises:
forming a first conductive pillar on and electrically coupled to a third bond pad on the first side of the first die; and
encapsulating the first die, the second die, and the first conductive pillar with a first encapsulant.

12. The method of claim 11 , wherein forming the first package further comprises:
forming an electrical connector over a carrier substrate;
attaching the bonded first and second dies to the carrier substrate adjacent the electrical connector, the first die being adjacent the carrier substrate;
encapsulating the bonded first and second dies, the first encapsulant, and the electrical connector with a second encapsulant; and
forming a first redistribution structure over the first die, the second die, the first encapsulant, the second encapsulant, and the electrical connector, the first redistribution structure being electrically coupled to the first conductive pillar and the electrical connector.

13. The method of claim 12 further comprising:
removing the carrier substrate; and
bonding a second package to the electrical connector of the first package using a first conductive connector, the second package being proximate the first die.

14. The method of claim 10 , wherein forming the first package further comprises:
forming a via in the first die;
encapsulating the first die and the second die with a first encapsulant;
forming an electrical connector over a carrier substrate;
attaching the encapsulant and bonded first and second dies to the carrier substrate adjacent the electrical connector, the second die being adjacent the carrier substrate;
encapsulating the bonded first and second dies, the first encapsulant, and the electrical connector with a second encapsulant;
planarizing the encapsulant, wherein after planarizing the electrical connector and the via in the first die are exposed;
forming a first redistribution structure over the first die, the second die, the first encapsulant, the second encapsulant, and the electrical connector, the first redistribution structure being electrically coupled to the via in the first die and the electrical connector; and
forming conductive connectors over and electrically coupled to the first redistribution structure.

15. The method of claim 10 , wherein the first insulating layer and the second insulating layer are both made of a polymer.

16. The method of claim 10 , wherein the first insulating layer and the second insulating layer are both made of silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or a combination thereof.

17. A method comprising:
forming a first insulating layer over a first side of a first wafer;
patterning a recess in the first insulating layer;
conformally depositing a conductive material in the recess and over the first insulating layer, a thickness of the conductive material being less than a thickness of the first insulating layer;
removing portions of the conductive material outside of the recess to form a first bond pad, the first bond pad and the first insulating layer being on a first active side of a first die in the first wafer, wherein after the removing, a top surface of the first bond pad is level with a top surface of the first insulating layer;
forming a second die comprising a second active side, the second active side comprising a second bond pad and a second insulating layer;
forming a conductive bump on the second bond pad, the conductive bump having a reflow temperature lower than reflow temperatures of the first and second bond pads;
bonding the conductive bump on t

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Tung Chih-Hang
• Yee Kuo-Chung

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title